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Description: Arbiter.v verilog实现
三路请求,使用循环策略的仲裁器
含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
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Size: 2048 |
Author: 夏虫 |
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Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
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Size: 12288 |
Author: maliang |
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Description: IC设计相关,arm内的AMBA桥实现的源码,verilog语言实现,-IC design, arm within the realization of the source AMBA bridge, verilog language,
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Size: 18432 |
Author: 伊路发 |
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Description: amba3 sva 完全验证的代码,有verilog的和systemverilog的-amba3 sva fully validate the code, and the Verilog and SystemVerilog
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Size: 280576 |
Author: kevin |
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Description: AMBA总线规范_cn_V1[1].0-中文翻译-AMBA bus specification _cn_V1 [1] .0- Chinese translation
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Size: 1095680 |
Author: 刘建明 |
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Description: AMBA总线AHB TO AHB bridge-AMBA bus AHB TO AHB bridge
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Size: 2048 |
Author: xiaoheng |
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Description: this is a code of AMBA AHB master protocol in verilog
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Size: 1024 |
Author: bhaskar |
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Description: amba ahb master decoder
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Size: 1024 |
Author: bhaskar |
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Description: AMBA AXI资料,台湾硕士论文,网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
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Size: 1288192 |
Author: kyle |
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Description: 基于APB总线的uart控制器,包括源码和vcs脚本-UART controller based on AMBA APB
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Size: 7168 |
Author: Samuel Xu |
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Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
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Size: 198656 |
Author: guoxiaojin |
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Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
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Size: 209920 |
Author: guoxiaojin |
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Description: amba总线桥:ahb to asb!verilog hdl文档加代码,非常全,soc-amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
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Size: 165888 |
Author: zhangyiyun |
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Description: amba with arm processor description and use
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Size: 458752 |
Author: srivastavsandy |
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Description: AMBA AHB verilog Source code
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Size: 195584 |
Author: Frank Chen |
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Description: It s the verilog source code for AMBA APB 2.0 Slave
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Size: 4096 |
Author: nachi |
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Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
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Size: 196608 |
Author: nodeity |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: 一个apb总线控制8253的verilog源代码,符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
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Size: 107520 |
Author: 蔡搏 |
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Description: AMBA总线的verilog实现,AMBA是ARM limited 公司推出的一种为嵌入式系统所设计的总线协议。-AMBA bus Verilog, AMBA bus protocol is the the of ARM limited company launched a embedded system design.
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Size: 2048 |
Author: 汪波 |
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