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[VHDL-FPGA-Verilog] adma.tar

Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Platform: | Size: 12288 | Author: maliang | Hits:

[Other] AMBA_cn_V1[1].0

Description: AMBA总线规范_cn_V1[1].0－中文翻译-AMBA bus specification _cn_V1 [1] .0- Chinese translation
Platform: | Size: 1095680 | Author: 刘建明 | Hits:

[Other] ahb2ahb

Description: AMBA总线AHB TO AHB bridge-AMBA bus AHB TO AHB bridge
Platform: | Size: 2048 | Author: xiaoheng | Hits:

[Windows Develop] System_Design_and_Implementation_of_AXI_Bus

Description: AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
Platform: | Size: 1288192 | Author: kyle | Hits:

[VHDL-FPGA-Verilog] AHB_SRRAM

Description: SSRAM with AHB bus interface source code
Platform: | Size: 205824 | Author: nan | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
Platform: | Size: 198656 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: | Size: 209920 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] AHBtoAPB

Description: amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc-amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
Platform: | Size: 165888 | Author: zhangyiyun | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] a_vhdl_8253_timer_latest.tar

Description: 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
Platform: | Size: 107520 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现-iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation
Platform: | Size: 463872 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[Other] AMBA

Description: AMBA总线的verilog实现，AMBA是ARM limited 公司推出的一种为嵌入式系统所设计的总线协议。-AMBA bus Verilog, AMBA bus protocol is the the of ARM limited company launched a embedded system design.
Platform: | Size: 2048 | Author: 汪波 | Hits:

[VHDL-FPGA-Verilog] APB_slave

Description: APB slave template for AMBA bus written in Verilog
Platform: | Size: 1024 | Author: corgano | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
Platform: | Size: 17408 | Author: zhch26 | Hits:

[MiddleWare] abma

Description: Verilog/VHDL AHB AMBA BUS Arch.
Platform: | Size: 508928 | Author: jooho | Hits:

[VHDL-FPGA-Verilog] apb.v

Description: AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
Platform: | Size: 805888 | Author: 卧室一条鱼 | Hits:

[VHDL-FPGA-Verilog] AMBA_VIP

Description: AMBA 总线IP 核Verilog代码(AMBA bus IP Verilog code)
Platform: | Size: 79872 | Author: 逐末 | Hits:

[VHDL-FPGA-Verilog] axi_slave

Description: amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
Platform: | Size: 1024 | Author: 过客3944 | Hits:

[] ahb_sram

Description: amba总线的ahb到sram的接口，Verilog代码，还算详细，算是不错的资料。(The AHB to SRAM interface of the AMBA bus)
Platform: | Size: 329728 | Author: zzf仗剑天涯 | Hits:

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