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[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870400 | Author: 李楠 | Hits:

Description: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Platform: | Size: 468992 | Author: 张 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[File Format] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60416 | Author: 刘彦 | Hits:

[Other Embeded program] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175104 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] dac

Description: DAC converter design with Verilog code and testbench
Platform: | Size: 527360 | Author: 田磊 | Hits:

[VHDL-FPGA-Verilog] I2C_HDL

Description: I2C bus HDL source and testbench
Platform: | Size: 701440 | Author: liuKe | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
Platform: | Size: 348160 | Author: horse | Hits:

[VHDL-FPGA-Verilog] rom_table

Description: rom vector table vhdl and Testbench
Platform: | Size: 172032 | Author: KoBin | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[Other] alu

Description: ALU modeling verilog codes and testbench
Platform: | Size: 545792 | Author: neorome | Hits:

[Other] HDL_CHIP_DESIGN[1]

Description: 介绍了如何编写正确且有效的vhdl/verilog hdl testbench,详细讲解了仿真测试程序的编写-Describes how to write correct and effective vhdl/verilog hdl testbench, explained in detail the preparation of the simulation test procedure
Platform: | Size: 5524480 | Author: neo | Hits:

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[Crack Hack] rom_des

[VHDL-FPGA-Verilog] flash接口控制_verilog

[Other] 《Verilog黄金指南》中文翻译版

[VHDL-FPGA-Verilog] generic_fifo

[VHDL-FPGA-Verilog] sram

[File Format] verilog_testbench_preliminary

[Other Embeded program] FIFO_v

[VHDL-FPGA-Verilog] dac

[VHDL-FPGA-Verilog] I2C_HDL

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] rom_table

[VHDL-FPGA-Verilog] fifo

[Other] alu

[Other] HDL_CHIP_DESIGN[1]

[VHDL-FPGA-Verilog] ssram-and-tesebench

[VHDL-FPGA-Verilog] Modsim-AND-testbench

[Other] shift-register-and-testbench

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] frequency divider and testbench

[VHDL-FPGA-Verilog] Uart-Verilog

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