Description: the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication. Platform: |
Size: 56320 |
Author:王琪 |
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Description: verilog程序,实现两个16bit数乘法,采用booth算法,基于状态机实现,分层次为datapath和controller两个子模块,testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test Platform: |
Size: 2048 |
Author: |
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Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed. Platform: |
Size: 4096 |
Author:lanty |
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Description: 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code Platform: |
Size: 1024 |
Author:lixiang |
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Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
-A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. Platform: |
Size: 7168 |
Author:Michael Lee |
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Description: 16位booth乘法器的实现:先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中,由最低位与虚拟位开始,一次判定两位,会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, starting from the lowest and the virtual position, determine the two time, there will be 4 kinds of results.) Platform: |
Size: 1024 |
Author:药
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Description: Booth乘法器是属于位操作乘法器,采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.) Platform: |
Size: 2138112 |
Author:wlkid1412 |
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