Search - verilog clock

Search - verilog clock - List

[Embeded-SCM Develop] verilog-clock DL : 0: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Update : 2008-10-13 Size : 1.69kb Publisher : 李瑞
[Embeded-SCM Develop] verilog-clock DL : 0: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Update : 2025-02-17 Size : 1kb Publisher : 李瑞
[VHDL-FPGA-Verilog] Verilog DHL数字钟 DL : 0: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Update : 2025-02-17 Size : 2kb Publisher : 谢树扬
[MPI] clock DL : 1: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Update : 2025-02-17 Size : 2kb Publisher : 吴俊泉
[VHDL-FPGA-Verilog] clock DL : 0: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Update : 2025-02-17 Size : 320kb Publisher : lg
[Program doc] clock DL : 0: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
Update : 2025-02-17 Size : 10kb Publisher : 王忠
[VHDL-FPGA-Verilog] clock DL : 0: dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
Update : 2025-02-17 Size : 78kb Publisher : pp
[SCM] Verilog(clock) DL : 0: 用VERILOG语言编写的电子钟程序.是用GW48教学实验箱仿真-Verilog language using an electronic bell procedures. GW48 is teaching me the experimental simulation
Update : 2025-02-17 Size : 7kb Publisher : 阿洪
[VHDL-FPGA-Verilog] Clock DL : 0: 用Verilog 实现的电子时钟，给初学者一个模版，学习Verilog。-Using Verilog realize an electronic clock, a template for beginners to learn Verilog.
Update : 2025-02-17 Size : 11kb Publisher : Jason
[Windows Develop] clock DL : 0: 实现时钟的计时、报时功能，verilog实现。-To achieve time clock, timekeeping functions, verilog achieve.
Update : 2025-02-17 Size : 719kb Publisher : 杨卫
[Other] CLOCK DL : 0: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Update : 2025-02-17 Size : 178kb Publisher : 张保平
[VHDL-FPGA-Verilog] clock DL : 0: 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
Update : 2025-02-17 Size : 1kb Publisher : 黄建
[VHDL-FPGA-Verilog] verilog DL : 0: 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language description of quarters II-based platforms
Update : 2025-02-17 Size : 7kb Publisher : lvlv
[ARM-PowerPC-ColdFire-MIPS] clock DL : 0: simple clock over verilog
Update : 2025-02-17 Size : 1kb Publisher : kennic chan
[VHDL-FPGA-Verilog] clock DL : 0: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Update : 2025-02-17 Size : 2.96mb Publisher : 陈涵
[Other] verilog DL : 0: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Update : 2025-02-17 Size : 17kb Publisher : ddr
[VHDL-FPGA-Verilog] clock DL : 0: verilog hdl代码实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
Update : 2025-02-17 Size : 2kb Publisher : Along
[VHDL-FPGA-Verilog] clock DL : 0: verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Update : 2025-02-17 Size : 1kb Publisher : Tuyan
[VHDL-FPGA-Verilog] Verilog DL : 0: verilog digital clock
Update : 2025-02-17 Size : 12kb Publisher : mini
[VHDL-FPGA-Verilog] Clock generator DL : 0: A clock Generator in verilog
Update : 2025-02-17 Size : 1kb Publisher : sadii

« 12 3 4 5 6 7 8 9 10 ... 31 »