Search - verilog code PWM

Search - verilog code PWM - List

[Embeded-SCM Develop] pwm发生器 DL : 0: pwm发生器（原理图,pcb，程序流程图，源码80kc196）--PWM generator, including diagram, pcb, data flow diagram , and source code 80kc196).
Update : 2025-02-17 Size : 64kb Publisher : 张晓亮
[VHDL-FPGA-Verilog] Source DL : 0: PWM的Verilog HDL代码用于FPGA-PWM of the Verilog HDL code for FPGA
Update : 2025-02-17 Size : 2kb Publisher : 张猛蛟
[VHDL-FPGA-Verilog] 76_PID DL : 0: 一个非常好的电机转速控制器VHDL源代码设计-A very good motor speed controller VHDL design source code
Update : 2025-02-17 Size : 2kb Publisher : linew
[VHDL-FPGA-Verilog] FPGA_PWM DL : 0: 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple modification to the application!
Update : 2025-02-17 Size : 1kb Publisher : 温海龙
[SCM] Source DL : 0: PWM Verilog源代码，可以通过仿真测试-PWM Verilog source code, can be tested through simulation
Update : 2025-02-17 Size : 2kb Publisher : shuichengwen
[VHDL-FPGA-Verilog] lai_PWM DL : 0: FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
Update : 2025-02-17 Size : 847kb Publisher : huangyongbing
[VHDL-FPGA-Verilog] pwm_hw DL : 0: sopc nios ii学习资料介绍niosii 开发自定义外设pwm的verilog源代码-Learning sopc nios ii information on the development of custom peripherals niosii the verilog source code pwm
Update : 2025-02-17 Size : 4kb Publisher : 顾勇
[SCM] pwm DL : 0: pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Update : 2025-02-17 Size : 1kb Publisher : chenhaoran
[VHDL-FPGA-Verilog] fpga-pwm DL : 1: 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Update : 2025-02-17 Size : 1.11mb Publisher : 黄家武
[Audio program] audio_up8sample DL : 0: verilog代码。利用音频信号上采样8倍，然后对audio做pwm调制。-verilog code.upsample audio date 8 times and output pwm of audio.
Update : 2025-02-17 Size : 11kb Publisher : eastwall
[VHDL-FPGA-Verilog] PWM_moto_ctrl DL : 0: verilog 代码实现直流电机PWM控制内有整个完整工程和modelsim仿真文件-verilog code for PWM DC motor control to achieve within the whole integrity of engineering and modelsim simulation files
Update : 2025-02-17 Size : 927kb Publisher : 文一左
[VHDL-FPGA-Verilog] pwm DL : 0: PWM脉冲产生代码，程序采用VHDL硬件描述语言！很有参考价值-PWM pulse generation code, the program using VHDL hardware description language! Useful reference
Update : 2025-02-17 Size : 75kb Publisher : 周涛
[VHDL-FPGA-Verilog] pwm DL : 0: 适合初学者对PWM调制的学习，解释比较明确，由于来元于核心程序，功能强大-Enables the keyboard scan code in Verilog source code, clear for beginners Comments
Update : 2025-02-17 Size : 2kb Publisher : 上关蓝乡
[VHDL-FPGA-Verilog] PWM DL : 0: 基于FPGA的PWM的一小段代码！用VERILOG 写的，主要是控制一盏led灯的亮度问题-Based on FPGA PWM of small pieces of code! VERILOG with written, main is to control a lamp that led lamp brightness problem
Update : 2025-02-17 Size : 2.89mb Publisher : zhangyuguang
[VHDL-FPGA-Verilog] PWM DL : 0: PWM IP 核的verilog HDL代码-CODE of the PWM IP
Update : 2025-02-17 Size : 1kb Publisher : mr li
[VHDL-FPGA-Verilog] pwm DL : 0: 乒乓球实验的VERILOG源代码。XILINX spartan6.-Table Tennis experiment VERILOG source code. XILINX spartan6.
Update : 2025-02-17 Size : 1kb Publisher : Yang Chenguang
[Other] pwm DL : 0: pwm波的verilog源代码，非常实用-pwm wave verilog source code, very useful
Update : 2025-02-17 Size : 345kb Publisher : lwh
[Software Engineering] AVALON_PWM_B DL : 0: L利用verilog编写的PWM代码，易于理解-L using the PWM verilog code written and easy to understand
Update : 2025-02-17 Size : 1kb Publisher : 张慧霞
[VHDL-FPGA-Verilog] PWM DL : 0: 通过设置时钟实现脉冲宽度调制的verilog代码及测试(By setting the clock to achieve pulse width modulation of the Verilog code and test)
Update : 2025-02-17 Size : 152kb Publisher : 老虎szjwl
[VHDL-FPGA-Verilog] deadzone DL : 0: 代码功能是实现脉冲信号的死区控制。根据输入脉冲实现10us的死区，避免IGBT直通。(The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.)
Update : 2025-02-17 Size : 1kb Publisher : FollowSky

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