Search - verilog code for leds

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[VHDL-FPGA-Verilog] code DL : 0: Verilog的LED控制器源程序，用于LED显示屏幕的控制。-Verilog source code of the LED controller for the LED display screen control.
Date : 2025-07-06 Size : 2kb User : 王
[VHDL-FPGA-Verilog] Sevenseg DL : 0: verilog code for a decoder that converts bcd to seven segment leds
Date : 2025-07-06 Size : 23kb User : z
[Other] verilog DL : 0: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Date : 2025-07-06 Size : 17kb User : ddr
[Other] seven_seg_decoder DL : 0: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no.
Date : 2025-07-06 Size : 1kb User : hassan
[VHDL-FPGA-Verilog] S9_LED_RUN DL : 0: 用Verilog语言编写的用于驱动led灯-this is a code for drive leds in verilog
Date : 2025-07-06 Size : 162kb User : 王景波
[VHDL-FPGA-Verilog] 145103015 DL : 0: Verilog source code for using keypad module with zybo fpga board to take input and show output to onboard leds and led module connected to GPIO
Date : 2025-07-06 Size : 1019kb User : abdelrahman