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[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Platform: | Size: 776192 | Author: 汪旭 | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[VHDL-FPGA-Verilog] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8192 | Author: leigh lee | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[VHDL-FPGA-Verilog] idt71v416s10

Description: code for ram in verilog hdl
Platform: | Size: 2048 | Author: Oleg | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] ram

Description: verilog 编写的ram代码，开发环境为quartus-ram write verilog code development environment for quartus
Platform: | Size: 2053120 | Author: li | Hits:

[VHDL-FPGA-Verilog] ram_sp_ar_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_sp_sr_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_dp_sr_sw.v

Description: this is a verilog source code for Dual Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] syncram

Description: verilog rtl and testbench code for single port sync ram
Platform: | Size: 1024 | Author: murali krishna | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[Education soft system] Domain Specific Hardware Accelerators: Vector Processing Units

Description: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are implemented in Bluespec System Verilog: CPU RAM Bus Vector Processor CPU A minimal 2 stage pipelined inorder processor. Vector Processor A vector processor capable of: Vector Negation (int8, int16, int32, float32) Vector Minima (int8, int16, int32, float32)
Platform: | Size: 3301613 | Author: nalevihtkas | Hits:

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