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[VHDL-FPGA-Verilog] scramble

Description: 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。-Communication scrambling circuit VHDL Code
Platform: | Size: 1024 | Author: 江山 | Hits:

[Communication] verilog_scramble.v.tar

Description: 扰码程序，利用Verilog语言实现，适合各种通信系统的扰码。-scramble code,verilog hdl,adapt to many communication systems
Platform: | Size: 1024 | Author: daiyingchun | Hits:

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