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[Crack Hack] aes_core

Description: Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Platform: | Size: 79872 | Author: yuansuchun | Hits:

[VHDL-FPGA-Verilog] SerialtoParallelConverter

Description: 串行转并行SerialtoParallelConverter-Serial to Parallel SerialtoParallelConverter
Platform: | Size: 26624 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] parallel_to_serial

Description: 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据-A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
Platform: | Size: 153600 | Author: 梅博 | Hits:

[VHDL-FPGA-Verilog] SERDES

Description: 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] SinPout

Description: FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
Platform: | Size: 237568 | Author: wicoboy | Hits:

[VHDL-FPGA-Verilog] seria-to-parallel

Description: 主要用来实现数据串并转换功能，内附2种实现程序-serial to parallel converter verilog code
Platform: | Size: 1024 | Author: 徐以为 | Hits:

[VHDL-FPGA-Verilog] I2S-Serial-communication

Description: 这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
Platform: | Size: 5048320 | Author: 小林 | Hits:

[VHDL-FPGA-Verilog] FPGA__source-code__Verilog

Description: FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Including triggers, full adder, divider, and parallel to serial conversion, counter, sequencer and other Verilog language source code.
Platform: | Size: 1908736 | Author: 张秋爽 | Hits:

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