Search - verilog convolutional

Search - verilog convolutional - List

[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k DL : 0: 卷积码编码和维特比解码当K为7 时供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Update : 2025-02-17 Size : 248kb Publisher : 周小川
[VHDL-FPGA-Verilog] crc_16 DL : 0: 利用verilog实现的一个（2,1,2）卷积码的编码器,很有用的哟!-Verilog realize the use of a (2,1,2) convolutional code encoder, yo useful!
Update : 2025-02-17 Size : 1kb Publisher : 刘横
[Communication] viterbidecoder DL : 0: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。-2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
Update : 2025-02-17 Size : 1.59mb Publisher : Wayne
[VHDL-FPGA-Verilog] BCDconv DL : 0: BCD编码的Verilog HDL程序，能够实现BCD编码与卷积码。-BCD-coded Verilog HDL procedures, to achieve BCD encoding and convolutional codes.
Update : 2025-02-17 Size : 107kb Publisher : 张明
[VHDL-FPGA-Verilog] 219encode DL : 0: （219）卷积编码的verilog hdl源代码,很有用的啊,-(219) convolutional coding verilog hdl source code, very useful, ah,
Update : 2025-02-17 Size : 1kb Publisher : 骆军
[VHDL-FPGA-Verilog] viterbi DL : 0: (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
Update : 2025-02-17 Size : 10kb Publisher : rxl
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Update : 2025-02-17 Size : 250kb Publisher : mediative
[VHDL-FPGA-Verilog] Convolution DL : 0: Update : 2025-02-17 Size : 102kb Publisher : 龚阳
[Communication-Mobile] viter2 DL : 0: verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
Update : 2025-02-17 Size : 8kb Publisher : 张洪
[Other] interleaver DL : 0: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Update : 2025-02-17 Size : 2kb Publisher : tomsontiger
[VHDL-FPGA-Verilog] conv_enc DL : 0: 这是一个用VERILOG HDL编写的卷积码程序-This is a VERILOG HDL with the preparation of procedures for the convolutional codes
Update : 2025-02-17 Size : 1kb Publisher : chenxiaoming
[Communication-Mobile] fangzhen DL : 0: 卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
Update : 2025-02-17 Size : 16kb Publisher : 小小
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Update : 2025-02-17 Size : 3kb Publisher : xiongherui
[VHDL-FPGA-Verilog] interleaver DL : 0: 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
Update : 2025-02-17 Size : 63kb Publisher : Yang Jie
[VHDL-FPGA-Verilog] conv_enc DL : 0: 该程序文档是用verilog实现卷积码的编码和解码，报告中从原理进行详细的分析，代码程序也有详细的备注-The program document is to achieve convolutional code with verilog coding and decoding, the report analysises the principle ,the code also has a detailed program note.
Update : 2025-02-17 Size : 212kb Publisher : 飞扬奇迹
[VHDL-FPGA-Verilog] Viterbi_verilog DL : 0: 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
Update : 2025-02-17 Size : 4.88mb Publisher : lxz
[VHDL-FPGA-Verilog] VerilogHDL DL : 0: 基于verilog convolutional coding 的卷积编码-verilog convolutional coding
Update : 2025-02-17 Size : 167kb Publisher : xks
[VHDL-FPGA-Verilog] verilog-juanjima DL : 1: 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast.
Update : 2025-02-17 Size : 10kb Publisher : 邓博于、
[MPI] nvdla-vmod DL : 0: 卷积神经网络实现的参考,借助于英伟达的开源硬件加速器。(Convolutional neural network reference, with open source hardware accelerator in nvidia.)
Update : 2025-02-17 Size : 3.76mb Publisher : ensureglitte
[VHDL-FPGA-Verilog] Hardware-CNN-master DL : 0: Convolutional neural network code for fpga
Update : 2025-02-17 Size : 293kb Publisher : anand97

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