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Description: verilog实例 100 多个-more than 100 examples of Verilog
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Size: 189440 |
Author: 地方 |
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Description: 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
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Size: 10240 |
Author: 刘波 |
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Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
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Size: 121856 |
Author: 于飞 |
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Description: 能综合的YCrCb2RGB模块(verilog)_采用3级流水线,用fpga做小数运算,还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
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Size: 1024 |
Author: 于飞 |
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Description: CRC校验码,用于对数据流进行crc校验。
主要有CRC_16,CRC_8,CRC_32校验。
所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
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Size: 10240 |
Author: 李鹏 |
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Description: 循环冗余校验,crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
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Size: 31744 |
Author: 李鹏 |
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Description: 写CRC编解码程序时,整理的文件,压缩文件既有理论说明,也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
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Size: 706560 |
Author: cdl |
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Description: 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
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Size: 47104 |
Author: way |
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Description: CRC循环校验码的VERILOG源文件,在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
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Size: 26624 |
Author: 刘仪 |
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Description: 比较完善的CRC编码VerilogHDL描述-more perfect description of CRC coding VerilogHDL
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Size: 4096 |
Author: nil |
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Description: 此是进行循环冗余效验的Verilog编码,适合多种标准,如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
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Size: 3072 |
Author: 藏瑞 |
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Description: 一个verilog实现的crc校验,用于fpga实现,快速,准确有效-A Verilog realize the CRC checksum for the FPGA realization, rapid, accurate and effective
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Size: 1440768 |
Author: 枫叶鹏 |
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Description: 用Verilog编写crc校验码,包括8位,12位,16位,32位,非常实用-Prepared using Verilog CRC check codes, including 8, 12, 16, 32, a very practical
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Size: 11264 |
Author: asd |
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Description: 用于10M,100M,1000M以太网的并行CRC算法,有别于一般的CRC算法。verilog描述-For 10M, 100M, 1000M Ethernet parallel CRC algorithm, the CRC algorithm is different from the ordinary. Verilog Description
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Size: 1024 |
Author: winwalk |
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Description: verilog 实现循环冗余校验
源代码-Cyclic Redundancy Check realize Verilog source code
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Size: 367616 |
Author: 长空 |
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Description: Verilog写的 CRC 编码-CRC code written in Verilog
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Size: 1024 |
Author: 孔祥 |
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Description: CRC-16 VHDL Source Code
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Size: 164864 |
Author: kobin |
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Description: verilog crc source code
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Size: 1024 |
Author: aa45646 |
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Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
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Size: 60416 |
Author: badfox |
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Description: For implementing the CRC in verilog or VHDL
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Size: 100352 |
Author: test |
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