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[Other resource] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3800 | Author: 藏瑞 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言
Platform: | Size: 1127 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3072 | Author: 樊文杰 | Hits:

[VHDL-FPGA-Verilog] rece_7E

Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写-HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Platform: | Size: 2048 | Author: 刘彻 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[VHDL-FPGA-Verilog] crc16_8

Description: crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
Platform: | Size: 1024 | Author: chenk | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
Platform: | Size: 6144 | Author: 吴伟珍 | Hits:

[VHDL-FPGA-Verilog] jjm

Description: 用Verilog实现的crc16编码器，可以实现任意长度帧的发送信息的crc无失真编码-Implemented with Verilog crc16 encoder can send frames of any length lossless coding of information crc
Platform: | Size: 199680 | Author: 陆翔 | Hits:

[VHDL-FPGA-Verilog] CRC16

Description: 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
Platform: | Size: 3072 | Author: 栾磊 | Hits:

[VHDL-FPGA-Verilog] crc16

Description: x16+x12+x5+1 verilog
Platform: | Size: 1024 | Author: 刘倩茹 | Hits:

[VHDL-FPGA-Verilog] crc16-

Description: 本文档描述了一种CRC校验的方法，开发语言为verilog。程序自己写的，包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
Platform: | Size: 1024 | Author: 秦艳召 | Hits:

[Other] crc_16

Description: RFID标签 CRC16校验实现,判断传输的正确性，实现完整的传输校验功能，Verilog编程实现。-CRC16 verilog technology
Platform: | Size: 1024 | Author: 凌楠 | Hits:

[Other] crc16CCITT

Description: 自己用verilog编写的crc16-ccitt码的产生，是并行的。-Crc16-ccitt code written in verilog generate parallel.
Platform: | Size: 191488 | Author: 解夏敏 | Hits:

[VHDL-FPGA-Verilog] jiaoyan

Description: Verilog编写的crc16校验程序，为大家通信校验提供一种可靠的方法-Verilog prepared crc16 checksum procedure for everyone to provide a reliable communication method validation
Platform: | Size: 351232 | Author: 李子豪 | Hits:

[VHDL-FPGA-Verilog] FPGA_CRC

Description: 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source code, and the principles of my hand calculations. This program has been ModelSim-Altera simulation, simulation waveform files are in this document.
Platform: | Size: 1191936 | Author: yuantielei | Hits:

[VHDL-FPGA-Verilog] CRC16_V

Description: 基于Verilog的CRC16实现，已在altera FPGA验证通过-Based on the CRC16 Verilog implementation, has been verified in FPGA Altera.
Platform: | Size: 1583104 | Author: liven | Hits:

[Other] crc_write

Description: 基于quartus II的CRC16校验代码，并实现了Modlsim实现了仿真验证(The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim)
Platform: | Size: 50087936 | Author: hay_123 | Hits:

[VHDL-FPGA-Verilog] crc16

Description: verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)
Platform: | Size: 3072 | Author: suncrystal | Hits:
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