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[VHDL-FPGA-Verilog] 200632146671689

Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
Platform: | Size: 741376 | Author: lele | Hits:

[VHDL-FPGA-Verilog] verilog_Divide

Description: 这是我下的一个用verilog实现的除法代码-This is the one I use to achieve the verilog code division
Platform: | Size: 7168 | Author: | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ALU

Description: ALU可以实现16种操作（包括加减乘除移位运算等）-ALU can be 16 kinds of operations (including addition and subtraction multiplication and division shift operator, etc.)
Platform: | Size: 838656 | Author: 草野彰 | Hits:

[VHDL-FPGA-Verilog] cpu(FinalWithYS)

Description: verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
Platform: | Size: 8192 | Author: 鲁迪 | Hits:

[VHDL-FPGA-Verilog] division_cordic

Description: verilog code for division based on cordic algorithm
Platform: | Size: 1024 | Author: meysam | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

[Crack Hack] rsa

Description: 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
Platform: | Size: 2384896 | Author: 齐娜 | Hits:

[VHDL-FPGA-Verilog] division

Description: Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
Platform: | Size: 4096 | Author: RQG | Hits:

[VHDL-FPGA-Verilog] fpu_div

Description: verilog code floating point division
Platform: | Size: 2048 | Author: Nikhil | Hits:

[VHDL-FPGA-Verilog] verilog-Division-calculation

Description: verilog Division calculation verilog 除法计算方法-verilog Division calculation
Platform: | Size: 254976 | Author: liu | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
Platform: | Size: 1024 | Author: 李家緯 | Hits:

[VHDL-FPGA-Verilog] Odd-number-frequency-division

Description: 在FPGA中对系统时钟进行奇数分频程序，可适当改变参数对其进行任意奇数分频 verilog HDL语言-Odd number frequency division program based on FPGA
Platform: | Size: 336896 | Author: yzy | Hits:

[VHDL-FPGA-Verilog] division-verilog

Description: 文章详解介绍了用Verilog HDL语言编写任意倍偶数分频和奇数分频的原理以及源程序，都通过仿真，结果完全正确。-The article introduced with sep Verilog HDL language writing any times frequency and the odd points even points of the principle and the frequency source program, through the simulation, the result completely correct.
Platform: | Size: 6144 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] verilog-codes

Description: bit segmentation in wide division code multiple ace-bit segmentation in wide division code multiple acess
Platform: | Size: 46080 | Author: prashant | Hits:

[VHDL-FPGA-Verilog] Division

Description: Verilog hdl 除法综合仿真实现，另包含测试文件-Verilog hdl Division
Platform: | Size: 1024 | Author: 杨凯 | Hits:

[VHDL-FPGA-Verilog] verilog-HDL-Divider

Description: 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
Platform: | Size: 1024 | Author: moxiaolin | Hits:

[Other] random frenquency division

Description: verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
Platform: | Size: 1024 | Author: qq956179683 | Hits:

[Documents] verilog分享--verilog快速掌握之模块例化

Description: 快速掌握verilog实例化分享程序，对于使用verilog编写的固件，需要功能划分，体现实例化的用处，便于归档提取，以备再次使用(Quickly grasp the Verilog instantiation sharing program, for the use of Verilog firmware, the need for functional division, to reflect the usefulness of instantiation, easy to archive extraction, for re use)
Platform: | Size: 185344 | Author: qing wang | Hits:
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