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[Embeded-SCM Develop] verilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181085 | Author: 吴旭辉 | Hits:

[Other resource] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
Platform: | Size: 359836 | Author: 任学 | Hits:

[Embeded-SCM Develop] verilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181248 | Author: 吴旭辉 | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] Ultraedit_verilog

Description: 这个文件中提供了 verilog hdl 的在ultra edit32中编程所需要的语法-This document provides a verilog hdl in ultra edit32 programming required in grammar
Platform: | Size: 30720 | Author: 陈轩辕 | Hits:

[Editor] Verilog_golden

Description: Verilog_golden中文版.pdf -Verilog_golden中文版.pdfVerilog_golden中文版.pdf
Platform: | Size: 468992 | Author: 肖鑫 | Hits:

[VHDL-FPGA-Verilog] jianyijiafaqi

Description: 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
Platform: | Size: 1090560 | Author: 阿凡提 | Hits:

[VHDL-FPGA-Verilog] UpDownCounter

Description: This is an Up Down Counter coded in Verilog HDL. You can edit the bus width of this.
Platform: | Size: 6419456 | Author: Patrick Go | Hits:

[VHDL-FPGA-Verilog] Norflash

Description: 用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。-Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.
Platform: | Size: 215040 | Author: 黄光奇 | Hits:

[Software Engineering] clock

Description: 这是紫外光通信PPM调制设计系统中的时钟信号设置。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is the clock signal in the PPM modulation design of ultraviolet communication system Settings. Edit and compile successfully with Verilog language, hope to help everyone
Platform: | Size: 49152 | Author: wm | Hits:

[Software Engineering] crcb

Description: 这是紫外光通信PPM调制设计系统中的信道编码程序设计。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is the channel coding in the PPM modulation design of ultraviolet communication system programming. Edit and compile successfully with Verilog language, hope to help everyone
Platform: | Size: 69632 | Author: wm | Hits:

[Software Engineering] d16to4

Description: 这是紫外光通信PPM调制设计系统中的16位数据转换为4位数据程序设计。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is 16 PPM modulation design of ultraviolet communication system of the four data programming. Edit and compile successfully with Verilog language, hope to help everyone
Platform: | Size: 63488 | Author: wm | Hits:

[Software Engineering] ppmt

Description: 这是紫外光通信PPM调制设计系统中的PPM原理程序设计。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is the principle of PPM in the PPM modulation design of ultraviolet communication system programming. Edit and compile successfully with Verilog language, hope to help everyone
Platform: | Size: 49152 | Author: wm | Hits:

[VHDL-FPGA-Verilog] pic10

Description: 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好 PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考 PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file. Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks There are three documents: PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference PIC10F: PIC10 family of microcontrollers
Platform: | Size: 3458048 | Author: Eddie | Hits:

[Linux driver] ad9854_drive_64bits

Description: ad9854 verilog程序代码,初学者编辑，上传供大家学习参考-ad9854 verilog code, for beginners to edit, upload for everyone to learn reference
Platform: | Size: 165888 | Author: 郭征 | Hits:

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