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[Other resource] filter 代码

Description: 用verilog实现滤波器的功能，通过软件综合仿真，在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
Platform: | Size: 221966 | Author: 龙明 | Hits:

[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] filter 代码

Description: 用verilog实现滤波器的功能，通过软件综合仿真，在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
Platform: | Size: 222208 | Author: 龙明 | Hits:

[VHDL-FPGA-Verilog] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26624 | Author: QQ | Hits:

[Special Effects] MedianFilter33

Description: 3*3 中值滤波的verilog代码实现，已经调试通过！欢迎提出宝贵意见！-3* 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!
Platform: | Size: 49152 | Author: | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。 -Verilog procedures, to achieve 4-order filter fir-filter.
Platform: | Size: 1024 | Author: 左麟 | Hits:

[MPI] dmf_pn_catch

Description: 采用匹配滤波，实现伪码捕获功能，模块内部可以产生简单噪声来验证捕获性能(verilog)-Matched filter used to achieve pseudo-code capture functionality, the module can generate simple internal noise to verify the performance capture (verilog)
Platform: | Size: 2673664 | Author: 曹旸 | Hits:

[VHDL-FPGA-Verilog] hbf-da-timeshare

Description: This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).
Platform: | Size: 22528 | Author: | Hits:

[VHDL-FPGA-Verilog] median

Description: 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
Platform: | Size: 1775616 | Author: yuming | Hits:

[source in ebook] cic512

Description: 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证，一、具有很高的速率-5-order CIC filter, collected 12 times the Verilog procedures are by simulation, one with a very high rate
Platform: | Size: 1024 | Author: xiebin | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] verilog.DA.FIR..

Description: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Platform: | Size: 576512 | Author: 代鑫 | Hits:

[Embeded-SCM Develop] 18a

Description: 匹配滤波器设计，VERILOG实现的，比较好的哦-Matched filter design, VERILOG implementation, and better oh
Platform: | Size: 51200 | Author: 洪依 | Hits:

[Energy industry] Verilog

Description: 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Platform: | Size: 3072 | Author: 田静 | Hits:

[Software Engineering] FIR

Description: FIR filter using verilog code
Platform: | Size: 2150400 | Author: Karama | Hits:

[VHDL-FPGA-Verilog] filter

Description: 如何利用verilog设计数字滤波器 包含低通滤波器,带通滤波器,高通滤波器.-how to design a digit filter with Verilog
Platform: | Size: 3245056 | Author: jefferson | Hits:

[VHDL-FPGA-Verilog] 3-3-median-filter

Description: verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
Platform: | Size: 51200 | Author: | Hits:

[VHDL-FPGA-Verilog] digital-filter

Description: Verilog语言综合的固定频率的数字滤波器，用于滤除夹杂在固定频率信号上的杂波信号，包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
Platform: | Size: 215040 | Author: 张秋光 | Hits:

[e-language] filter

Description: 数字滤波器的verilog语言程序，为双精度的滤波器，可以实现10k低通滤波-verilog filter
Platform: | Size: 7168 | Author: meng | Hits:

[VHDL-FPGA-Verilog] hp and lp filter

Description: hp and lp filter verilog code..
Platform: | Size: 3072 | Author: GIRISH | Hits:
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