Search - verilog frequency counter

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[VHDL-FPGA-Verilog] verilogclock DL : 0: 如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
Date : 2025-07-19 Size : 3kb User :
[VHDL-FPGA-Verilog] counter DL : 0: verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
Date : 2025-07-19 Size : 142kb User : chen
[VHDL-FPGA-Verilog] Verilog--shiyanbaogao DL : 0: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三利用条件语句实现计数分频时序电路实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。练习四阻塞赋值与非阻塞赋值的区别实验目的： 1．通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2．了解阻塞赋值与非阻塞赋值的不同使用场合； 3．学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
Date : 2025-07-19 Size : 15kb User : 盼盼
[Software Engineering] pld DL : 0: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数；分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率；请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Date : 2025-07-19 Size : 31kb User : 李侠
[VHDL-FPGA-Verilog] freqm DL : 0: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Date : 2025-07-19 Size : 12kb User : wangfeng
[VHDL-FPGA-Verilog] counter DL : 0: 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
Date : 2025-07-19 Size : 2.46mb User : double
[Other] frequencycounter DL : 0: 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
Date : 2025-07-19 Size : 2kb User : zhangliang
[VHDL-FPGA-Verilog] Cymometer DL : 0: Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Date : 2025-07-19 Size : 572kb User : 石头
[VHDL-FPGA-Verilog] counter DL : 0: 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
Date : 2025-07-19 Size : 2kb User : tangxiaolei
[VHDL-FPGA-Verilog] digital-frequency DL : 0: 数字频率计采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
Date : 2025-07-19 Size : 1.21mb User : multidecoder
[VHDL-FPGA-Verilog] Fre_Counter_verilog DL : 0: 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
Date : 2025-07-19 Size : 1.09mb User : yunhen
[VHDL-FPGA-Verilog] pinlvji DL : 0: 自己编的一个频率计，verilog语言写的，用数码管显示方波的频率，测量量程是0.1hz~9999999hz，测方波的稳定性极高。-Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square wave test.
Date : 2025-07-19 Size : 1.36mb User : 龙德勇
[VHDL-FPGA-Verilog] verilogClassicSamples DL : 0: verilog常用程序及其仿真结果整理，包括LCD，LED，AD采集，URAT，电子琴，电梯控制，自动售货机控制，出租车计价器，电子时钟，频率计，MPSK调制与解调-verilog common finishing process and its simulation results, including LCD, LED, AD collection, URAT, keyboard, elevator control, vending machine control, taxi meter, electronic clock, frequency counter, MPSK modulation and demodulation, etc.
Date : 2025-07-19 Size : 1.22mb User : ZhangYan
[VHDL-FPGA-Verilog] verilog DL : 0: 基于QUATEUS2的设计一个8位频率计verilog语言编程-The design is based QUATEUS2 an 8-bit frequency counter verilog programming language
Date : 2025-07-19 Size : 3.48mb User : 雷亚庆
[VHDL-FPGA-Verilog] Frequency DL : 0: 频率计，用verilog编写。语言简洁易懂。-Frequency counter, written in verilog.
Date : 2025-07-19 Size : 1.55mb User : 王赢之
[Other] Frequency-meter DL : 0: 用Verilog语言编写的频率计，可以精确到1Hz-Frequency counter with the Verilog language, can be accurate to 1Hz
Date : 2025-07-19 Size : 13kb User : 李炜
[Compress-Decompress algrithms] frequency-counter DL : 0: 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompression can be directly downloaded to the DE2 board, in which the frequency of the input of the system comes with 27M clock D13 used for testing If you want to apply to other development board can reassign pin.
Date : 2025-07-19 Size : 601kb User : 予烨
[Home Personal application] digital-frequency-counter DL : 0: 基于FPGA的数字频率计，verilog hdl编写-digital frequency counter ，using verilog hdl
Date : 2025-07-19 Size : 17kb User : 毋宁
[Other] frequency-meter---DEII DL : 0: verilog写的频率计，在数码管上显示10进制输入数字信号的频率。已在DEII上验证- verilog write frequency counter, decimal display frequency of the input digital signal in the digital tube. Verified on DEII
Date : 2025-07-19 Size : 266kb User : 孔沛瑶
[Other] FreqCounter_1_12 DL : 0: verilog code on frequency counter
Date : 2025-07-19 Size : 8kb User : kasun

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