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[Other resource] hamming.tar

Description: verilog 实现的hamming码生成，用于fpga
Platform: | Size: 6348 | Author: 枫叶鹏 | Hits:

[Other resource] hamming.tar

Description: Verilog语言实现的Hamming(3,7)编码器，可用于FPGA实现
Platform: | Size: 6498 | Author: 陈楚龙 | Hits:

[VHDL-FPGA-Verilog] hamming_decoder

Description: 汉明编码和解码的VHDL程序，直接解压就可以了-Hamming encoding and decoding process of VHDL, can be directly extracted a
Platform: | Size: 1024 | Author: 李成军 | Hits:

[VHDL-FPGA-Verilog] hamming.tar

Description: verilog 实现的hamming码生成，用于fpga-Verilog realize the Hamming code generated for the FPGA
Platform: | Size: 6144 | Author: 枫叶鹏 | Hits:

[VHDL-FPGA-Verilog] hamming.tar

Description: Verilog语言实现的Hamming(3,7)编码器，可用于FPGA实现-Verilog Language realize the Hamming (3,7) encoder, can be used to realize FPGA
Platform: | Size: 6144 | Author: 陈楚龙 | Hits:

[VHDL-FPGA-Verilog] Ham_Code

Description: Hamming code is implemented by ASIC design method.-With verilog design way, we can check error control code with hamming code .
Platform: | Size: 9216 | Author: ananliu1 | Hits:

[VHDL-FPGA-Verilog] hanming

Description: 用Verilog语言实现汉明编码，很粗燥，是大三的时候做的-With the Verilog language Hamming code, it is rough dry, a junior at the time to do
Platform: | Size: 1024 | Author: xiaohuai | Hits:

[VHDL-FPGA-Verilog] ass1_2_hamming

Description: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Platform: | Size: 1133568 | Author: wei chenghao | Hits:

[VHDL-FPGA-Verilog] ecc

Description: For implementing the Hamming coding in verilog or VHDL
Platform: | Size: 132096 | Author: test | Hits:

[VHDL-FPGA-Verilog] hamming_encodeadecode

Description: 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.
Platform: | Size: 308224 | Author: 周杰奏 | Hits:

[VHDL-FPGA-Verilog] Hamming

Description: 汉明码转换，在FPGA上用verilog实现-hamming encoder, using FPGA
Platform: | Size: 408576 | Author: leaffloat | Hits:

[VHDL-FPGA-Verilog] Hamming32

Description: It has a simple verilog code to calculate 32 bit hamming distance and a test bench to simulate.
Platform: | Size: 1024 | Author: hdl_explorer | Hits:

[VHDL-FPGA-Verilog] non_ham_en_decoder

Description: 不组帧汉明编码/解码，Verilog语言实现，带仿真程序。 -No framing hamming encoding/decoding, Verilog language, with the simulation program.
Platform: | Size: 3072 | Author: 张刚 | Hits:

[VHDL-FPGA-Verilog] Error-Correcting-For-7bit-Hamming-Code

Description: Verilog Module for a 3 to 8 bit decoder
Platform: | Size: 84992 | Author: Raz | Hits:

[VHDL-FPGA-Verilog] decode

Description: 用Verilog实现汉明码编码，经测试可正确使用，代码简洁-Verilog with Hamming code encoding, the test can be used correctly, the code is simple
Platform: | Size: 23552 | Author: Lay | Hits:

[VHDL-FPGA-Verilog] decode

Description: 用Verilog实现汉明码的解码，经测试可以正常使用，且代码简介-Verilog with Hamming code to achieve the decoding, the test can be used normally, and the code
Platform: | Size: 23552 | Author: Lay | Hits:

[VHDL-FPGA-Verilog] hamming

Description: verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
Platform: | Size: 49736704 | Author: 嵩山独坐 | Hits:

[VHDL-FPGA-Verilog] ECC

Description: 基于汉明码的ECC纠错算法，可纠错1位，供参考(An ECC error correction algorithm based on hamming code can be used for reference)
Platform: | Size: 1024 | Author: 一粒尘埃 | Hits:

[VHDL-FPGA-Verilog] haming

Description: 汉明码编解码程序，便于初学者掌握verilog HDL语言的组合逻辑电路设计原则(Hamming code encoding and decoding program is easy for beginners to master the design principles of combinational logic circuits of Verilog HDL language.)
Platform: | Size: 4176896 | Author: victorfan2017 | Hits:

[VHDL-FPGA-Verilog] Hamming-ECC-master

Description: HI THAT IS DOC AND CODE FOR HAMMING CODE
Platform: | Size: 30720 | Author: nano1 | Hits:
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