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Description: 基于verilog HDL的自动售货机控制电路设计:
可以对5种不同种类的货物进行自动售货,价格分别为A=1.00,B=1.50,C=1.80,D=3.10,E=5.00 。售货机可以接受1元,5角,1角三种硬币(即有三种输入信号IY,IWJ,IYJ),并且在一个3位7段LED(二位代表元,一位代表角)显示以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出,选择货物的输入信号Ia,Ib,Ic,Id,Ie和一个放弃信号In,输出指示信号为 Sa, Sb ,Sc ,Sd, Se 分别表示售出相应的货物,同时输出的信号yuan, jiao代表找零,相应每个脉冲代表找零相应的硬币，上述输入和输出信号均是一个固定宽度的脉冲信号。
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Size: 1776 |
Author: chenyi |
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Description: 基于verilog HDL的自动售货机控制电路设计:
可以对5种不同种类的货物进行自动售货,价格分别为A=1.00,B=1.50,C=1.80,D=3.10,E=5.00 。售货机可以接受1元,5角,1角三种硬币(即有三种输入信号IY,IWJ,IYJ),并且在一个3位7段LED(二位代表元,一位代表角)显示以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出,选择货物的输入信号Ia,Ib,Ic,Id,Ie和一个放弃信号In,输出指示信号为 Sa, Sb ,Sc ,Sd, Se 分别表示售出相应的货物,同时输出的信号yuan, jiao代表找零,相应每个脉冲代表找零相应的硬币，上述输入和输出信号均是一个固定宽度的脉冲信号。
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Size: 1024 |
Author: chenyi |
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Description: IEEE standard Verilog HDL1364-2001.pdf
Verilog 学习必备资料-IEEE standard Verilog HDL1364-2001.pdfVerilog learning essential information
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Size: 2174976 |
Author: 洪磊 |
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Description: 一种基于verilog HDL的自动售货机控制电路设计:能对5种不同种类的货物进行自动售货，价格分别为A=1.00，B=1.50，C=1.80，D=3.10，E=5.00 。售货机能接受1元，5角，111角三种硬币(即有三种输入信号IY，IWJ，IYJ)，并且在一个3位7段LED(二位代表元，一位代表角)显示出来以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出，选择货物的输入信号I
-Verilog HDL-based vending machine control circuit design: vending of five different kinds of goods, prices were A = 1.00, B = 1.50, C = 1.80, the D = 3.10, E = 5.00. Vending machines can accept $ 1, 5 angle, 111 angle of three kinds of coins (ie, three types of input signal IY, IWJ, IYJ), and a three 7-segment LED (two representatives, a representative of the angle) displayed the total amount of money invested, up 9.90 yuan, if greater than this value, the coins of the new input will exit, select the input signal of the goods
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Size: 2048 |
Author: 清醒 |
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Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
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Size: 600064 |
Author: 饕餮小宇 |
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Description: 实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure
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Size: 2048 |
Author: 桑梓 |
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