Search - verilog ieee

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[Other resource] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE DL : 0: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Update : 2008-10-13 Size : 371.9kb Publisher : 王刚
[Other resource] verilog-ieee DL : 0: verilog ieee standard 2001
Update : 2008-10-13 Size : 2.07mb Publisher : liang
[Books] verilog 黄金手册 DL : 0: verilog HDL IEEE标准手册。很不错，可以做手册参考。
Update : 2009-06-01 Size : 272.37kb Publisher : raini135792
[Other Embeded program] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE DL : 0: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar-IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Update : 2025-02-17 Size : 372kb Publisher : 王刚
[Other] verilog-ieee DL : 0: verilog ieee standard 2001
Update : 2025-02-17 Size : 2.07mb Publisher : liang
[Internet-Network] IEEE_standard_Verilog_HDL1364_2001 DL : 0: IEEE standard Verilog HDL1364-2001.pdf Verilog 学习必备资料-IEEE standard Verilog HDL1364-2001.pdfVerilog learning essential information
Update : 2025-02-17 Size : 2.07mb Publisher : 洪磊
[VHDL-FPGA-Verilog] FPGAREAL DL : 0: 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems.
Update : 2025-02-17 Size : 301kb Publisher : 卓智海
[VHDL-FPGA-Verilog] Verilog DL : 1: 很不错的Verilog 书籍，包括ieee标准和黄金指南-Very good Verilog books, including ieee standards and Gold Guide
Update : 2025-02-17 Size : 3.24mb Publisher : haiwaw
[Other] Kluwer.The.Verilog.Hardware.Description.Language.5 DL : 1: Verilog硬件描述语言，第五版 Thomas&Moorby等著。权威的Verilog介绍，包含IEEE-1364 2001 标准 -The Verilog® Hardware Description Language, Fifth Edition. By Thomas&Moorby
Update : 2025-02-17 Size : 6.86mb Publisher : Jasper Hu
[Other] verilog-ieee DL : 0: verilog 2001 LRM.IEEE standard.
Update : 2025-02-17 Size : 2.08mb Publisher : muylor
[Software Engineering] IEEE_Verilog_2001 DL : 0: Verilog 2001 编程规范中文版，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
Update : 2025-02-17 Size : 2.13mb Publisher : 徐杰猛
[Other] verilog-ieee2001 DL : 0: verilog IEEE标准，学verilog必须要看的资料，将近800页，非常推荐-verilog IEEE standards, learning verilog have to look at the data, nearly 800 pages, very recommended
Update : 2025-02-17 Size : 2.07mb Publisher : huizi
[Software Engineering] verilog-ieee DL : 0: verilog introduction
Update : 2025-02-17 Size : 2.07mb Publisher : Nguyen Trong Tri
[VHDL-FPGA-Verilog] IEEE.Standard.Verilog.Hardware.Description.Languag DL : 0: IEEE Standard Verilog Hardware Description Language-IEEE Standard Verilog Hardware Description Language(
Update : 2025-02-17 Size : 2.08mb Publisher : liukai
[File Format] verilog-ieee.pdf.tar DL : 0: IEEE 2001 verilog 标准 ,详细讲述了业内公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.
Update : 2025-02-17 Size : 2.1mb Publisher : adam
[Software Engineering] Verilog-IEEE-Std(1364-2005) DL : 1: Verilog IEEE Std(1364-2005) 标准,硬件开发必备手册-Verilog IEEE Std (1364-2005) standards, hardware development of the necessary manual
Update : 2025-02-17 Size : 3.03mb Publisher : panqihe
[Other] 2005-Verilog-IEEE-Std(1364-2005) DL : 0: IEEE Standard for Verilog Hardware Description Language 1364-2005 verilog2005版本的标准-IEEE Standard for Verilog Hardware Description Language 1364-2005
Update : 2025-02-17 Size : 3.04mb Publisher : 赵先生
[Software Engineering] verilog-ieee DL : 0: The Verilog ¤ Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs the communication of hardware design data and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog HDL, Verilog PLI, Verilog ¤-The Verilog ¤ Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs the communication of hardware design data and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog HDL, Verilog PLI, Verilog ¤
Update : 2025-02-17 Size : 2.08mb Publisher : bkaraca
[VHDL-FPGA-Verilog] IEEE Standard for Verilog 2005 DL : 0: IEEE Standard for Verilog 2005
Update : 2025-02-17 Size : 2.99mb Publisher : zking
[VHDL-FPGA-Verilog] IEEE Standard for Verilog 2005 DL : 0: this book introduces the use of Verilog HDL.
Update : 2025-02-17 Size : 2.99mb Publisher : ^U^

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