Search - verilog jpeg fpga

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[Other resource] fpga-jpeg-verilog DL : 0: fpga-jpeg-verilog在fpga平台使用verilog语言进行jpeg算法实现
Update : 2008-10-13 Size : 101.8kb Publisher : yang
[Other resource] fpga-jpeg DL : 0: jepg verilog example
Update : 2008-10-13 Size : 101.66kb Publisher : 展望
[VHDL-FPGA-Verilog] JPEG2000_FPGA_Design DL : 0: 本论文主要论述JPEG2000中嵌入式块编码的FPGA设计，非常有参考价值-this paper mainly discusses JPEG2000 coding embedded blocks of FPGA design, a very valuable reference
Update : 2025-02-17 Size : 757kb Publisher : 周辉
[Software Engineering] huawei DL : 0: 华为FPGA设计流程指南，FPGA设计者、项目管理者必读的文档，看看别人是怎么做的。-Huawei FPGA design flow guide, FPGA designers, project managers must-read documents, take a look at how others do.
Update : 2025-02-17 Size : 31kb Publisher : 贺雷
[Other Embeded program] fpga-jpeg-verilog DL : 0: fpga-jpeg-verilog在fpga平台使用verilog语言进行jpeg算法实现-fpga-jpeg-verilog FPGA platform used in the Verilog language Algorithm jpeg
Update : 2025-02-17 Size : 102kb Publisher : yang
[VHDL-FPGA-Verilog] djpeg.tar DL : 0: jpeg格式到bmp格式的硬件实现，verilog开发，fpga 实现。-jpeg format to bmp format hardware realize, verilog development, fpga realize.
Update : 2025-02-17 Size : 178kb Publisher : 枫叶鹏
[VHDL-FPGA-Verilog] fpga-jpeg DL : 0: jepg verilog example
Update : 2025-02-17 Size : 101kb Publisher : 展望
[VHDL-FPGA-Verilog] DCT_IDCT DL : 0: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Update : 2025-02-17 Size : 29kb Publisher : caesar
[VHDL-FPGA-Verilog] huffman DL : 0: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 10kb Publisher : caesar
[VHDL-FPGA-Verilog] quant DL : 0: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 14kb Publisher : caesar
[VHDL-FPGA-Verilog] iquant DL : 0: Update : 2025-02-17 Size : 13kb Publisher : caesar
[VHDL-FPGA-Verilog] rle DL : 0: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 4kb Publisher : caesar
[VHDL-FPGA-Verilog] zigzag DL : 0: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤盲禄炉脣茫篓渭脛HDL 卤脿脗毛拢卢掳眉脌篓 VHDL 录掳 Verilog
Update : 2025-02-17 Size : 7kb Publisher : caesar
[VHDL-FPGA-Verilog] zigzag_decode DL : 0: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 3kb Publisher : caesar
[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog) DL : 0: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Update : 2025-02-17 Size : 1.19mb Publisher : chenlu
[VHDL-FPGA-Verilog] jpegVerilog DL : 0: FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
Update : 2025-02-17 Size : 102kb Publisher : 许伟
[VHDL-FPGA-Verilog] fpga_jpeg DL : 0: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Update : 2025-02-17 Size : 101kb Publisher : 沧海一笑
[VHDL-FPGA-Verilog] Chapter6-9 DL : 0: 第六章到第九章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update : 2025-02-17 Size : 5.99mb Publisher : xiao
[VHDL-FPGA-Verilog] VERILOG-jpeg DL : 0: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Update : 2025-02-17 Size : 101kb Publisher : ken
[VHDL-FPGA-Verilog] fpga-jpeg-verilog DL : 0: fpga实现jpeg压缩，和视频采集程序-fpga jpeg
Update : 2025-02-17 Size : 102kb Publisher : guqiutao

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