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[Applications] manchester DL : 0: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Update : 2008-10-13 Size : 4.03kb Publisher : 刘波
[Communication-Mobile] 曼彻斯特编解码Verilog代码 DL : 0: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
Update : 2008-10-13 Size : 9.81kb Publisher : 崔广辉
[Applications] manchester DL : 0: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Update : 2025-02-17 Size : 4kb Publisher : 刘波
[Communication-Mobile] 曼彻斯特编解码Verilog代码 DL : 0: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
Update : 2025-02-17 Size : 10kb Publisher : 崔广辉
[VHDL-FPGA-Verilog] manchester_verilog DL : 0: 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Update : 2025-02-17 Size : 9kb Publisher : 李无志
[VHDL-FPGA-Verilog] 用cpld实现曼彻斯特编码 DL : 0: 用cpld实现曼彻斯特编码用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Update : 2025-02-17 Size : 4kb Publisher : 李鹏
[VHDL-FPGA-Verilog] man_Verilog DL : 0: 曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
Update : 2025-02-17 Size : 9kb Publisher : 刘超
[VHDL-FPGA-Verilog] NRZ_2_Manchester DL : 0: NRZ码到Manchester转换器 verilog-NRZ code to Verilog converter Manchester
Update : 2025-02-17 Size : 1kb Publisher : leysion
[VHDL-FPGA-Verilog] mancheester_v DL : 1: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Update : 2025-02-17 Size : 9kb Publisher : wangyunshann
[VHDL-FPGA-Verilog] manchester_verilog DL : 0: 曼彻斯特编解码Verilog代码非常好的速度快，而且资源占用少。 -Manchester codec Verilog code very good speed, but also occupy less resources.
Update : 2025-02-17 Size : 10kb Publisher : 王鹏
[VHDL-FPGA-Verilog] mcst DL : 0: 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
Update : 2025-02-17 Size : 1kb Publisher : yy
[MiddleWare] DifferentialManchestercodedecodingverilogcode DL : 0: 差分曼彻斯特码解码的verilog代码 -Differential Manchester code decoding verilog code
Update : 2025-02-17 Size : 1kb Publisher : 徐龙
[VHDL-FPGA-Verilog] manchester_verilog DL : 0: 用verilog写的一个manchester code的代码，含编解码-Used to write a verilog code for manchester code containing codec
Update : 2025-02-17 Size : 9kb Publisher : stream
[VHDL-FPGA-Verilog] Manchester DL : 0: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
Update : 2025-02-17 Size : 40kb Publisher : cst008
[VHDL-FPGA-Verilog] manchesterbyxilinx DL : 0: 曼彻斯特编解码的实现（Verilog）,包含有测试文件。-manchester encode and decode with verilog，Test File is included。
Update : 2025-02-17 Size : 10kb Publisher : cheuna
[VHDL-FPGA-Verilog] Manchester DL : 0: manchester coding verilog
Update : 2025-02-17 Size : 9kb Publisher : Jacknapes
[VHDL-FPGA-Verilog] manchester DL : 0: verilog 实现manchester编解码，最高速率5mhz-verilog manchester code to achieve the highest rate of 5mhz
Update : 2025-02-17 Size : 4kb Publisher : 王红星
[VHDL-FPGA-Verilog] mach_test_ok DL : 0: verilog曼切斯特编码解码的FPGA实现-verilog Manchester encoding and decoding on FPGA
Update : 2025-02-17 Size : 2kb Publisher : 朱
[VHDL-FPGA-Verilog] verilog DL : 0: 曼彻斯特编码的verilog实现,复制到quartus II可用-Manchester verilog realize the code,Copy to quartus II available
Update : 2025-02-17 Size : 10kb Publisher : 尹晋文
[VHDL-FPGA-Verilog] Manchester-Encoding-Verilog DL : 0: THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. -THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
Update : 2025-02-17 Size : 8kb Publisher : liyapei

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