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Description: 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
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Size: 47104 |
Author: way |
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Description: the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram- mt48lc2m32b2 d evice.
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Size: 6144 |
Author: nightyboy |
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Description: the verilog model of sram IS61LV25616AL device.-verilog model of the IS61LV25616AL de sram vice.
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Size: 24576 |
Author: nightyboy |
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Description: the verilog model of async_fifo.
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Size: 1024 |
Author: nightyboy |
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Description: iic 总线 verilog 源代码
标准i2c总线, 有sda scl 时钟,频率自定-IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-
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Size: 2048 |
Author: johnnyz |
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Description: Verilog based simluation model for MXIC SPI Flash.-err
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Size: 77824 |
Author: ronsullivan |
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Description: verilog model of a P-verilog model of a PLL
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Size: 135168 |
Author: jadedfox |
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Description: 三星SDRAM的verilog模型的完整源码-Verilog model of Samsung SDRAM complete source
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Size: 15360 |
Author: liu |
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Description: i2c总线从模式的verilog实现 适合研究i2c的同志参考-i2c bus from verilog model for study of the realization of comrades i2c reference
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Size: 5120 |
Author: chao |
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Description: verilog模型,用于仿真flash,可以快速地看懂-verilog model for flash controller
specified for spasion flash, please download it look at it
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Size: 226304 |
Author: jiangwen |
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Description: I2C EEPROM verilog simulation model
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Size: 634880 |
Author: Ravi |
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Description: I2C EEPROM verilog simulation model
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Size: 634880 |
Author: Ravi |
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Description: 三星flash编程Verilog程序,单页编程,支持K9K4G08芯片-Samsung' s flash programming Verilog program, single-page programming, support K9K4G08 chip
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Size: 1024 |
Author: 不知道 |
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Description: 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
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Size: 751616 |
Author: 陈少华 |
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Description: Altera DDR SDRAM控制器完整Verilog代码包,包括Verilog源代码,Doc说明文档,仿真DDR芯片模型,仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
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Size: 752640 |
Author: 沈志 |
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Description: 24xx02 Verilog Model 在官网上下载的 eepROM
可以参考-Download on the official website 24xx02 Verilog Model eepROM can refer to
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Size: 7168 |
Author: zcf287 |
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Description: berckley pipeline adc verilog model
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Size: 1457664 |
Author: beidawuxi123 |
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Description: a verilog model of universal seq detector
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Size: 159744 |
Author: Sasanka |
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Description: verilog model for 93xx6xx
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Size: 33792 |
Author: jwiggams
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Description: verilog model for 24xx04
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Size: 7168 |
Author: jwiggams
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