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[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包

Description: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Platform: | Size: 74752 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[Other] MODELSIM_learning

Description: 很好的VERILOG入门教程!个人感觉比Philip Moorby那本容易看懂-good VERILOG entry Guide! Philip personal feeling than the Moorby it easier to understand
Platform: | Size: 801792 | Author: 谢一 | Hits:

[VHDL-FPGA-Verilog] hamin0132

Description: 汉明码的编结码模块，用verilog写成，为Modelsim下的一个工程。-series guitar code modules, using Verilog languages, as Modelsim of a project.
Platform: | Size: 31744 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] crc3321

Description: CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
Platform: | Size: 26624 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] parity2258

Description: 奇偶校验码的VERILOG源码，为MODELSIM下的一个工程。有测试文件。-parity VERILOG source code for MODELSIM of a project. A test document.
Platform: | Size: 25600 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 1024 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[VHDL-FPGA-Verilog] multiple

Description: 介绍了几种常用的乘法器的设计，carry_save_mult，ripple_carry_mult等，压缩包中包含结构流程图，用verilogHDL语言，采用modelsim仿真验证-This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation
Platform: | Size: 266240 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。-Synchronous read write RAM verilog. Through simulation modelsim se.
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[Graph program] color_space_converters

Description: YCrCb到RGB的变换以及RGB到YCrCb的反变换，可用于视频采集等领域，verilog编码，modelsim验证-YCrCb to RGB and RGB to the YCrCb transform the inverse transform can be used in areas such as video capture, verilog coding, modelsim authentication
Platform: | Size: 7168 | Author: mayang | Hits:

[mpeg mp3] entropy_coding

Description: mpeg2视频压缩熵编码，verilog实现，modelsim仿真通过-mpeg2 video compression entropy coding, verilog realize, modelsim simulation through
Platform: | Size: 19456 | Author: mayang | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: modelsim 使用教程,verilog或vhdl仿真-ModelSim use tutorial, verilog or VHDL simulation
Platform: | Size: 487424 | Author: hxl | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] add

Description: 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Platform: | Size: 1024 | Author: 来法旧佛 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 用verilog编写的基于流水线结构的16阶滤波器的实现 -filter
Platform: | Size: 375808 | Author: 陈丽华 | Hits:

[Other] modelsim(chinese)

Description: modelsim是一款强大的仿真软件，针对verilog,vhdl设计进行全面调测-modelsim is a powerful simulation software for verilog, vhdl design of a comprehensive test tone
Platform: | Size: 539648 | Author: swb | Hits:

[VHDL-FPGA-Verilog] modelsim_6.3f_6.4b_6.5_crck

Description: 目前这个生成的key在modelsim se 6.3f 6.4b 6.5测试没问题。因为这几个版本是我逐步升级的，应该说从6.3f~6.5的都可以用。测试环境为windows xp sp3. vista没有测试。按理说是一样的。使用过程中遇到的一些问题的解决办法关于key里面生成中文字符的情况产生原因是，windows当前用户名和主机名是中文，修改之后重新生成一次。在安装的时候要设置环境变量LM_LICENSE_FILE，指向lincense的的路径和文件名。需要在cmd下使用modelsim的命令，需要将modelsim的win32目录添加到环境变量path中，这些都是EDA软件安装的一些基本常识了。对于modelsim的较新版本，会有提示。但是还要设置LM_LICENSE_FILE。 关于网卡号的设置可以使用-h的参数，更多参数请在命令行下使用-help来查看。 2009年9月14日测试支持最新的6.5C-modelsim se 6.3f 6.4b 6.5
Platform: | Size: 308224 | Author: yanghong | Hits:

[VHDL-FPGA-Verilog] ModelSim之命令行仿真入门

Description: 此文对modelsim的仿真命令进行了完整的总结，对于命令行仿真的初学者，非常有帮助(This article on the Modelsim simulation commands complete summary of the command line simulation for beginners, very helpful)
Platform: | Size: 2048 | Author: davidbmd | Hits:
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