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[Other resource] mult

Description: 64位乘法器源码verilog,经过验证测试
Platform: | Size: 60807 | Author: zhang chi | Hits:

[VHDL-FPGA-Verilog] mult

Description: 64位乘法器源码verilog,经过验证测试-64-bit multiplier source verilog, validated test
Platform: | Size: 60416 | Author: zhang chi | Hits:

[VHDL-FPGA-Verilog] MULT

Description: 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
Platform: | Size: 110592 | Author: 韩思贤 | Hits:

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] mult

Description: 这是一个mult源文件，用verilog语言写的，经过仿真正确。-This is a mult programm.
Platform: | Size: 4096 | Author: yuedongxu | Hits:

[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[VHDL-FPGA-Verilog] Designs

Description: design files in verilog, alu, array mult, carry shift etc.
Platform: | Size: 37888 | Author: p2p_123 | Hits:

[VHDL-FPGA-Verilog] mult

Description: 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
Platform: | Size: 2048 | Author: yolin | Hits:

[VHDL-FPGA-Verilog] mult

Description: 用verilog HDL语言实现的16位乘法器，以及tesrbench（测试文件）。-Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
Platform: | Size: 1024 | Author: jiyun | Hits:

[VHDL-FPGA-Verilog] multi_cycle_Verilog

Description: this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less than 32 bits in 32 clocks .
Platform: | Size: 4096 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] MULT

Description: the document used to describe the verilog codes design floating point multiplier in coms design
Platform: | Size: 2351104 | Author: rajapraba | Hits:

[VHDL-FPGA-Verilog] booth_mult

Description: 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] lut_mult

Description: 基于查找表的乘法器实现，verilog编写，Modelsim测试-use lut realize the mult
Platform: | Size: 1024 | Author: zhang | Hits:

[Software Engineering] ripple-carry-array-mult

Description: Ripple carry array multiplier design in verilog HDL
Platform: | Size: 1024 | Author: pravat | Hits:

[Software Engineering] carrysave-array-mult

Description: Carry save array multiplier design in verilog HDL
Platform: | Size: 1024 | Author: pravat | Hits:

[VHDL-FPGA-Verilog] MULT

Description: 用VERILOG实现乘法器功能，通过仿真验证-With VERILOG multiplier function is verified by simulation
Platform: | Size: 404480 | Author: 蚩建峰 | Hits:

[VHDL-FPGA-Verilog] mult

Description: verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
Platform: | Size: 1024 | Author: chrisxu | Hits:

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and modified paper output can be provided. Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
Platform: | Size: 783360 | Author: anandg | Hits:

[VHDL-FPGA-Verilog] mult-64bit-booth.txt

Description: 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
Platform: | Size: 94208 | Author: cunxi | Hits:

[Other] Mult

Description: this is multiplayer for verilog
Platform: | Size: 1024 | Author: Hainder | Hits:

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