Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog multi cycle

Search list

[Windows Develop] Multi_Cycle_Microprocessor_with_Control

Description: Multi Cycle processor with control logic Verilog Computer organization and design
Platform: | Size: 12288 | Author: Cho Hyun Woo | Hits:

[VHDL-FPGA-Verilog] multi_cpu

Description: 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
Platform: | Size: 5120 | Author: 阿月 | Hits:

[VHDL-FPGA-Verilog] multi_cpu

Description: 使用Verilog语言编写的多周期CPU,能实现CPU24条指令，-Using the Verilog language multi-cycle CPU, can achieve CPU24 instructions,
Platform: | Size: 1024 | Author: 洪鑫 | Hits:

[VHDL-FPGA-Verilog] MultiCLKCPU

Description: 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructions (see the source of specific instructions, not Kengren). Archive containing source code, program modules and test report forms and detailed design drawings, good material to learn verilog ah.
Platform: | Size: 6606848 | Author: 石 | Hits:

[Other] Multicycle

Description: verilog multi cycle. all modules
Platform: | Size: 2048 | Author: kjuh | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] MulticlockCPU.tar

Description: verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
Platform: | Size: 19317760 | Author: czl | Hits:

[VHDL-FPGA-Verilog] multi-cycle-MIPS

Description: multicycle-MIPS verilog implementation
Platform: | Size: 3072 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] multi_cycle_Verilog

Description: this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less than 32 bits in 32 clocks .
Platform: | Size: 4096 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd，rt，rs sra rd，rt，shamt blez rs, imm j target lwl rt，offset（base） lwr rt，offset（base） lw rt，imm（rs） sw rt，imm（rs） -Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
Platform: | Size: 5079040 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] MIPS-multi-cycle-(Quarters-II--Verillig)

Description: Multi cycle MIPS processor verilog
Platform: | Size: 2225152 | Author: zzang1323 | Hits:

[Other] mp2

Description: 用verilog 写的微程序多周期CPU.软件版本为10.1-Micro-program written in verilog. Multi-cycle CPU software version 10.1
Platform: | Size: 266240 | Author: zys | Hits:

[Software Engineering] mips--cpu

Description: 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic design and simulation tests using the Verilog language.
Platform: | Size: 314368 | Author: 朱祖建 | Hits:

[VHDL-FPGA-Verilog] dds_mul

Description: 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
Platform: | Size: 4069376 | Author: shanshan | Hits:

[VHDL-FPGA-Verilog] multi-CPU

Description: Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
Platform: | Size: 2049024 | Author: gtx | Hits:

[VHDL-FPGA-Verilog] multi_cpu

Description: 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
Platform: | Size: 2231296 | Author: 张宇轩 | Hits:

[VHDL-FPGA-Verilog] muCPU_final

Description: 用Verilog开发的多周期CPU,可执行mips汇编中的R\I\J型指令，具有较高的参考价值。-Using Verilog development of multi-cycle CPU, mips executable compilation of R \ I \ J-type instruction, with a high reference value.
Platform: | Size: 2060288 | Author: 孔晗聪 | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPSCPU

Description: 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
Platform: | Size: 169984 | Author: zhql945 | Hits:

[Other] multi_cpu

Description: 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
Platform: | Size: 1635328 | Author: chenjy | Hits:

[VHDL-FPGA-Verilog] start_lab4

Description: 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
Platform: | Size: 22189056 | Author: 林森 | Hits:
« 12 »

CodeBus www.codebus.net