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[VHDL-FPGA-Verilog] Verilog5

Description: 多工器ｖｅｒｉｌｏｇ設計1對多快速解碼提供控制功能-1 multiplexer Verilog design of multi-control functions to provide fast decoding
Platform: | Size: 244736 | Author: 蔡宗翰 | Hits:

[Other Embeded program] 4to1MUX

Description: Verilog code for 4 t0 1 multiplexer
Platform: | Size: 2048 | Author: wajahat | Hits:

[VHDL-FPGA-Verilog] veriloghdl

Description: 多路选择器（MUX）verilog hdl 多路选择器（MUX）verilog hdl-MUX (MUX) verilog hdl multiplexer (MUX) verilog hdl
Platform: | Size: 3072 | Author: 落木 | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Platform: | Size: 267264 | Author: kk | Hits:

[VHDL-FPGA-Verilog] mux

Description: the multiplexer program are designed 2:1 and 4:1 in verilog model
Platform: | Size: 1024 | Author: prabakaran | Hits:

[VHDL-FPGA-Verilog] digital-frequency

Description: 数字频率计 采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
Platform: | Size: 1265664 | Author: multidecoder | Hits:

[VHDL-FPGA-Verilog] adder2

Description: 此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.
Platform: | Size: 1024 | Author: 王柔毅 | Hits:

[VHDL-FPGA-Verilog] VerilogCode_8-bit_2to1_mux

Description: Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
Platform: | Size: 1024 | Author: Rahul | Hits:

[VHDL-FPGA-Verilog] 5-multiplexer

Description: five multiplexer, verilog, altera de2 board~
Platform: | Size: 2048 | Author: KYchocz | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[Software Engineering] codlab-17-2-12

Description: Verilog programs- multiplexer, encoder etc
Platform: | Size: 3072 | Author: YESHASWINI H.S | Hits:

[Program doc] verilog_example

Description: verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
Platform: | Size: 273408 | Author: 邹继超 | Hits:

[Software Engineering] CHU92A

Description: MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
Platform: | Size: 351232 | Author: he | Hits:

[ELanguage] mux2to1

Description: code for multiplexer in verilog
Platform: | Size: 1112064 | Author: harsha vardhan | Hits:

[Other Games] multiplexer

Description: Verilog Hardware descriptive language
Platform: | Size: 171008 | Author: mintoki | Hits:

[VHDL-FPGA-Verilog] FourToOneMux

Description: this is Implementation of 4 to 1 Multiplexer in verilog language for embedded design systems
Platform: | Size: 27648 | Author: Mood | Hits:

[Other] module multiplexer4

Description: Verilog code for multiplexer
Platform: | Size: 9216 | Author: maz1 | Hits:

[VHDL-FPGA-Verilog] Mrunal Mirani Verilog Assignment 1

Description: Multiplexer logic etc
Platform: | Size: 537600 | Author: ksureja | Hits:

[assembly language] Verilog源代码

Description: 多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.)
Platform: | Size: 18432 | Author: MMK1 | Hits:

[VHDL-FPGA-Verilog] DPWM

Description: 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
Platform: | Size: 500736 | Author: lw1997 | Hits:
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