Search - verilog nand

[SourceCode] micron m73a系列nand flash 芯片模型

Description: micron公司nand flash芯片m73a系列verilog仿真模型及测试代码
Platform: | Size: 85114 | Author: sucy03 | Hits:

[SDK] Samsung 8G x 8 Bit NAND Flash Memory SPEC & Simulatiom model

Description: Samsung 8G x 8 Bit NAND Flash Memory SPEC and verilog Simulatiom model
Platform: | Size: 1328527 | Author: asd12321 | Hits:

[VHDL-FPGA-Verilog] NAND256R3A_VE1

Description: 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
Platform: | Size: 203776 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[Other] verilog__nand

Description: verilog source code nand gate
Platform: | Size: 1024 | Author: hamsik yoo | Hits:

[VHDL-FPGA-Verilog] 4NandFlash

Description: 基于verilog hdl 的Nand Flash控制代码-Verilog hdl-based control code of the Nand Flash
Platform: | Size: 2048 | Author: wxd | Hits:

[FlashMX] Nand_verilog

Description: NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array. To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.-NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array. To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Platform: | Size: 870400 | Author: anirudhh | Hits:

[VHDL-FPGA-Verilog] NAND_IP

Description: Nand flash VHDL code and Nand flash verilog code
Platform: | Size: 22528 | Author: psungil | Hits:

[VHDL-FPGA-Verilog] MT29FxxG08xx

Description: MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。-MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed description, testing proved very accurate.
Platform: | Size: 92160 | Author: wuyihua | Hits:

[VHDL-FPGA-Verilog] Flash

Description: 三星flash编程Verilog程序，单页编程，支持K9K4G08芯片-Samsung' s flash programming Verilog program, single-page programming, support K9K4G08 chip
Platform: | Size: 1024 | Author: 不知道 | Hits:

[Other] altera_nand_controller

Description: Altera合作伙伴Eureka Technology.和Cast Inc.为Altera FPGA芯片定制的Nand flash controller IP core-Altera partner Eureka Technology. And the Cast Inc. For the Altera FPGA chip custom Nand flash controller IP core
Platform: | Size: 296960 | Author: Trevor | Hits:

[Multimedia program] l52a_nand_model

Description: 美光64GB nand flash 模型 verilog-micron 64GB nand flash verilog module
Platform: | Size: 64512 | Author: cancan | Hits:

[source in ebook] nand

Description: uso de compuertas nand para verilog
Platform: | Size: 2048 | Author: cris123 | Hits:

[VHDL-FPGA-Verilog] NAND_Flash_Controller

Description: FPGA实现的NandFlash控制器（带ECC）文档+源代码。-FPGA implementation NandFlash controller (with ECC) document+ source code.
Platform: | Size: 1587200 | Author: 李银 | Hits:

[VHDL-FPGA-Verilog] Verilogexample

Description: verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator-verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6 . The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator ....
Platform: | Size: 30720 | Author: vkiy | Hits:

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