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[VHDL-FPGA-Verilog] freq_meter

Description: Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
Platform: | Size: 667648 | Author: Nick | Hits:

[VHDL-FPGA-Verilog] seg

Description: 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
Platform: | Size: 1024 | Author: Along | Hits:

[VHDL-FPGA-Verilog] seg

Description: 用verilog语言实现数码管控制工作，有问题可以qq咨询，516998649-use the verilog language to drive the seg
Platform: | Size: 21504 | Author: badegg | Hits:

[VHDL-FPGA-Verilog] verilogiic1121

Description: i2c的verilog程序，通过写入eeprom再读出并在seg数码显示管上显示来进行验证-i2c' s verilog program eeprom read by writing out and in the seg digital display tube display to verify
Platform: | Size: 474112 | Author: zhangjian | Hits:

[VHDL-FPGA-Verilog] seg

Description: verilog编写的时钟分频程序和数码管显示程序-verilog
Platform: | Size: 40960 | Author: yinhailin | Hits:

[VHDL-FPGA-Verilog] seg

Description: 这是用verilog 编写的静态数码管实验，初级，实用，挺好的例程-It is written in verilog static digital test, primary, practical, very good routine
Platform: | Size: 3964928 | Author: blue | Hits:

[VHDL-FPGA-Verilog] 74HC595-seg

Description: 基于verilog语言的74HC595程序。两块74HC595联级使用-Based on the Verilog language 74HC595 procedures
Platform: | Size: 403456 | Author: 黄旭磊 | Hits:

[VHDL-FPGA-Verilog] 8-SEG-LED-Board

Description: 基于FPGA的EPM 1270芯片开发板的8 SEG LED Board Verilog程序，已通过测试，能正常使用，引脚已配好。-Based the EPM 1270 chip FPGA development board 8 SEG LED Board Verilog program has been tested normal use, the pin with a good.
Platform: | Size: 328704 | Author: 周涛 | Hits:

[VHDL-FPGA-Verilog] seg

Description: 大西瓜FPGA开发板陪赠资料\大西瓜FPGA开发板例程（基础+进阶）\开发板基础实验\开发板基础实验---数码管的动态显示。Verilog -Watermelon FPGA development board to accompany gifts Data \ the watermelon FPGA development board routines (foundation+ Advanced) \ basic experimental development board \ basic experimental development board--- digital tube dynamic display. Verilog
Platform: | Size: 373760 | Author: 飞飞法 | Hits:

[VHDL-FPGA-Verilog] SEG

Description: 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
Platform: | Size: 1024 | Author: 金纯 | Hits:

[VHDL-FPGA-Verilog] SEG7lED

Description: 基于verilog的7段数码管显示控制，实现数字显示。-7 seg led displaying control based on verilog
Platform: | Size: 4422656 | Author: 唐龙 | Hits:

[source in ebook] key

Description: PS2键盘协议代码 verilog，可以在ISE上跑，约束条件：NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14" NET"seg[1]" LOC="J17" NET"seg[0]" LOC="H14" NET"wei[0]" LOC="F17" NET"wei[1]" LOC="H17" NET"wei[2]" LOC="C18" NET"wei[3]" LOC="F15" NET"rx232_tx" LOC="P9" -PS2 keyboard verilog
Platform: | Size: 33792 | Author: 刘云 | Hits:

[VHDL-FPGA-Verilog] SegSimplified

Description: 本工程使用verilog HDL和vivado2014集成开发环境实现利用xilinx Basys3开发板上4位数码管显示从0到9999的计数器功能。-This project uses verilog HDL to realise counting 0 to 9999 on the 7-seg LED loaded on Xilinx Basys3 board.
Platform: | Size: 1210368 | Author: 姚罡 | Hits:

[transportation applications] traffic-light-Verilog

Description: 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights (each including+,- two groups, as the display contents), taking into account the needs of the application, the chip may be required It is connected to the host computer via the I2C interface, to adjust the internal control registers of this Verilog code, comprising led, seg, timer modules.
Platform: | Size: 16384 | Author: chen le | Hits:

[Other] BCDto7seg

Description: bcd to 7 seg code in verilog
Platform: | Size: 1024 | Author: tavakoli1374 | Hits:

[Embeded-SCM Develop] seg

Description: 基于verilog语言的74HC595程序,适用于驱动单个四位数码管(Four bit digital tube driver)
Platform: | Size: 1024 | Author: Lerry | Hits:

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