Description: SOURCE INSIGHT的verilog语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT verilog syntax of plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers Platform: |
Size: 3144 |
Author:洪炉 |
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Description: SOURCE INSIGHT的verilog语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT verilog syntax of plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers Platform: |
Size: 3072 |
Author:洪炉 |
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Description: Eda主要介绍的逻辑设计与集成电路：FPGA 设计的指导性原则（连载之二）
典型的FPGA 设计流程
大型复杂FPGA 设计推荐设计方式──Modular Design
Coding Style 与综合前后仿真
数据接口设计
关于有限状态机编码的技巧和注意事项
做distributed ram 时遇到的几个不太明白的信号
Source Insight 兼容VHDL 与VERILOG
如何实现信号延时？
[转载]新手学习技巧-EDA introduces the logical design of integrated circuits: FPGA design of the guiding principles (Part II)
Typical FPGA design flow
Large, complex FPGA design recommended design approach ─ ─ Modular Design
Coding Style and comprehensive before and after simulation
Data interface design
Finite state machine coding techniques and precautions
Do the Distributed RAM encountered a few do not quite understand the signal
Source Insight is compatible with VHDL and Verilog
How to achieve signal delay?
[Reserved] novice learning skills Platform: |
Size: 491520 |
Author:江风 |
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