Search - verilog spi cpld

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[Other resource] an485_design_example DL : 0: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Update : 2008-10-13 Size : 305.25kb Publisher : zhiqiang
[VHDL-FPGA-Verilog] an485_design_example DL : 0: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Update : 2025-02-17 Size : 305kb Publisher : zhiqiang
[SCM] mcu-cpld-spi DL : 0: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Update : 2025-02-17 Size : 108kb Publisher : 叶灿
[VHDL-FPGA-Verilog] SPI_IIC_design_example DL : 0: ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
Update : 2025-02-17 Size : 385kb Publisher : 郑康山
[VHDL-FPGA-Verilog] spi1 DL : 0: 使用verilog语言编写的实现cpld EPM570与EEPROM的SPI通信-Using verilog language to achieve cpld EPM570 SPI communication with the EEPROM
Update : 2025-02-17 Size : 2kb Publisher : LJL
[Com Port] receive_spi DL : 0: verilog语言SPI通信，可用于CPLD以及FPGA-Verilog language SPI communications, can be used for CPLD and FPGA
Update : 2025-02-17 Size : 1kb Publisher : 刘敏
[VHDL-FPGA-Verilog] tinycpufiles DL : 0: TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is a Quartus project, and it can run well on Altera MAXII CPLD, and it is conveniently change to other FPGAs. The CPU used 200 Logical Cells, and the device (peripherals such as SPI, LCD) used 180 Logical Cells. It also included a assembler source code (by VC2008), which can compile the asm file for the CPU.
Update : 2025-02-17 Size : 59kb Publisher : 肖海云
[Other] xapp386 DL : 0: SPI Implementation on CPLD
Update : 2025-02-17 Size : 3.06mb Publisher : Farook