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[Other resource] verilogfifo

Description: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Platform: | Size: 1412 | Author: zzm | Hits:

[Other resource] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16232 | Author: 田世坤 | Hits:

[Other resource] CPU

Description: 使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。
Platform: | Size: 43474 | Author: haotianr | Hits:

[VHDL-FPGA-Verilog] verilogfifo

Description: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Platform: | Size: 1024 | Author: zzm | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。
Platform: | Size: 43008 | Author: haotianr | Hits:

[VHDL-FPGA-Verilog] Ballastic_Calculator

Description: Ballastic Calculator Interface designe for Army TANK (Xilinx Verilog, Schematics)
Platform: | Size: 2699264 | Author: Tomahawk | Hits:

[Other] Memory

Description: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
Platform: | Size: 846848 | Author: Lokous | Hits:

[Other] Stack

Description: Implementation of 8 level deep stack in PIC1684fA using Verilog in structural mode
Platform: | Size: 17408 | Author: ayood | Hits:

[SCM] W5300_Driver_V1[1].1.1

Description: 硬件TCPIP协议栈芯片W5300的使用例子代码,该芯片内部通过硬件实现了TCPIP协议栈,可减少CPU运行协议栈的开销.-Hardware TCPIP protocol stack chips W5300 examples of the use of code, the chip hardware implementation of the internal adoption of the TCPIP protocol stack can reduce the CPU overhead of running the protocol stack.
Platform: | Size: 35840 | Author: hengdao | Hits:

[VHDL-FPGA-Verilog] b16

Description: 一个verilog实现的16位堆栈型处理器，实现了32条指令，fpga实现频率为26Mhz！-Verilog implementation of a 16-bit stack-based processor to realize the 32 instructions, fpga implementation frequency of 26Mhz!
Platform: | Size: 2048 | Author: JOY | Hits:

[VHDL-FPGA-Verilog] AFDX-end-system-based-on-FPGA-virtual-Implementati

Description: 基于FPGA的AFDX端系统协议栈虚链路层的研究与实现AFDX end system based on FPGA-virtual link layer protocol stack Research and Implementation-AFDX end system based on FPGA-virtual link layer protocol stack Research and Implementation
Platform: | Size: 480256 | Author: bala1234 | Hits:

[VHDL-FPGA-Verilog] udp_ip_stack_latest.tar

Description: UDP-IP stack with verilog hdl language from opnecores.org
Platform: | Size: 5028864 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] stack

Description: stack code for fpga..using verilog
Platform: | Size: 2048 | Author: mushi2020 | Hits:

[VHDL-FPGA-Verilog] sv

Description: stack and events in system verilog
Platform: | Size: 1024 | Author: Kiran | Hits:

[VHDL-FPGA-Verilog] Sdram_RD_FIFO

Description: 用SDRAM实现的读堆栈的verilog源代码-Read stack implemented SDRAM Verilog source code
Platform: | Size: 2048 | Author: 麦涛涛 | Hits:

[VHDL-FPGA-Verilog] Sdram_WR_FIFO

Description: 用SDRAM实现的写堆栈操作的verilog源代码-SDRAM write stack operations Verilog source code
Platform: | Size: 2048 | Author: 麦涛涛 | Hits:

[VHDL-FPGA-Verilog] flow_proc

Description: 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现 -In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation, the logic level signal decrease, increase frequency. The most vivid example is the bit width larger adder. This program is the realization of verilog
Platform: | Size: 229376 | Author: jodyql | Hits:

[VHDL-FPGA-Verilog] LIFO

Description: LIFO，先进后出缓冲器（栈），verilog源代码，包括测试代码。-LIFO, last-out buffer (stack), verilog source code, including test code.
Platform: | Size: 2048 | Author: 项中元 | Hits:

[VHDL-FPGA-Verilog] stack

Description: 根据堆栈逻辑结构，使用Verilog编写的一个堆栈，并通过仿真实现了功能-fist in last out
Platform: | Size: 4507648 | Author: 舒占军 | Hits:
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