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[Other resource] ref-sdr-sdram-verilog DL : 0: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Update : 2008-10-13 Size : 758.4kb Publisher : 汪旭
[Other resource] verilog-ieee DL : 0: verilog ieee standard 2001
Update : 2008-10-13 Size : 2.07mb Publisher : liang
[Other Embeded program] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE DL : 0: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar-IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Update : 2025-02-17 Size : 372kb Publisher : 王刚
[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL DL : 0: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Update : 2025-02-17 Size : 10kb Publisher : 于飞
[VHDL-FPGA-Verilog] arbit DL : 0: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Update : 2025-02-17 Size : 5kb Publisher : 宋昆仑
[VHDL-FPGA-Verilog] bidir DL : 0: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Update : 2025-02-17 Size : 4kb Publisher : 宋昆仑
[VHDL-FPGA-Verilog] 标准SDR SDRAM控制器参考设计_verilog_lattice DL : 0: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Update : 2025-02-17 Size : 199kb Publisher : 陈旭
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Update : 2025-02-17 Size : 758kb Publisher : 汪旭
[ARM-PowerPC-ColdFire-MIPS] ARMCORE DL : 0: 用verilog语言实现的ARM7处理器的标准内核的源代码程序,nnARM, 具有很好的参考价值-using Verilog language of the standard ARM7 processor core source code procedures nnARM, who have a good reference value
Update : 2025-02-17 Size : 447kb Publisher : 王晨语
[Documents] HDLCodingStyle DL : 0: verilog硬件描述语言编程规范，描述如何使你编写的代码的可读性更高，可用性更强，并且使你在编程过程中少犯一些低级错误。-Verilog hardware description language programming standard, and describe how you prepared to make the code more readable, more availability, and will enable you to the programming process less committed some minor errors.
Update : 2025-02-17 Size : 62kb Publisher :
[VHDL-FPGA-Verilog] trellis_verlog DL : 0: ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
Update : 2025-02-17 Size : 5kb Publisher : 刘超
[Other] verilog-ieee DL : 0: verilog ieee standard 2001
Update : 2025-02-17 Size : 2.07mb Publisher : liang
[Internet-Network] IEEE_standard_Verilog_HDL1364_2001 DL : 0: IEEE standard Verilog HDL1364-2001.pdf Verilog 学习必备资料-IEEE standard Verilog HDL1364-2001.pdfVerilog learning essential information
Update : 2025-02-17 Size : 2.07mb Publisher : 洪磊
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Update : 2025-02-17 Size : 758kb Publisher : 费尔德
[Special Effects] RGB2YCbCr DL : 1: JPEG标准中图像彩色空间的转换，开发语言为Verilog-Standard JPEG image color space conversion, the development of language for Verilog
Update : 2025-02-17 Size : 2kb Publisher : 卫立波
[VHDL-FPGA-Verilog] IEEE.Standard.Verilog.Hardware.Description.Languag DL : 0: IEEE Standard Verilog Hardware Description Language-IEEE Standard Verilog Hardware Description Language(
Update : 2025-02-17 Size : 2.08mb Publisher : liukai
[File Format] verilog-ieee.pdf.tar DL : 0: IEEE 2001 verilog 标准 ,详细讲述了业内公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.
Update : 2025-02-17 Size : 2.1mb Publisher : adam
[VHDL-FPGA-Verilog] fir10order-verilog DL : 0: 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
Update : 2025-02-17 Size : 70kb Publisher : wq
[VHDL-FPGA-Verilog] IEEE Standard for Verilog 2005 DL : 0: IEEE Standard for Verilog 2005
Update : 2025-02-17 Size : 2.99mb Publisher : zking
[VHDL-FPGA-Verilog] IEEE Standard for Verilog 2005 DL : 0: this book introduces the use of Verilog HDL.
Update : 2025-02-17 Size : 2.99mb Publisher : ^U^

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