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[Other resource] oc8051

Description: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Platform: | Size: 1227477 | Author: wutailiang | Hits:

[Other resource] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3242 | Author: 樊文杰 | Hits:

[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] oc8051

Description: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Platform: | Size: 1226752 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3072 | Author: 樊文杰 | Hits:

[VHDL-FPGA-Verilog] verilog_testbench_genetator

Description: 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as aaa.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------|
Platform: | Size: 2048 | Author: zishan | Hits:

[VHDL-FPGA-Verilog] Camera_Interface_Verilog

Description: 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating C code, the sdc and ucf files for the FPGA synthiese, help document.
Platform: | Size: 348160 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] mem

Description: 一种用于测试SRAM阵列的MARCH-C算法；使用Verilog语言描述，包括SRAM模块、MRACH-C算法还有testbench-An algorithm for MARCH-C test SRAM array using Verilog language description, including SRAM module, MRACH-C algorithms as well as testbench
Platform: | Size: 71680 | Author: 张云 | Hits:

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