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[VHDL-FPGA-Verilog] timer DL : 0: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Date : 2025-07-01 Size : 1kb User : 劉季泓
[VHDL-FPGA-Verilog] watch_dog_rtl_source DL : 0: Watchdog timer verilog RTL code
Date : 2025-07-01 Size : 10kb User : Chris
[VHDL-FPGA-Verilog] timer_rtl_source DL : 0: Timer verilog RTL code
Date : 2025-07-01 Size : 11kb User : Chris
[Other] verilog DL : 0: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Date : 2025-07-01 Size : 17kb User : ddr
[Other] gh_timer_8254_081608 DL : 0: Timer 8254 Verilog source code
Date : 2025-07-01 Size : 106kb User : Joe Hung
[Static control] LIP1701CORE_system_watchdog DL : 0: System watchdog verilog code
Date : 2025-07-01 Size : 281kb User : jc
[VHDL-FPGA-Verilog] time-counter DL : 0: 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
Date : 2025-07-01 Size : 2.44mb User : 张迪
[VHDL-FPGA-Verilog] digital-clock- DL : 0: 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
Date : 2025-07-01 Size : 158kb User : 西蟀
[VHDL-FPGA-Verilog] 24stimer DL : 0: 篮球24s定时器的verilog代码，内涵代码以及程序逻辑说明-basketball 24s timer code of verilog
Date : 2025-07-01 Size : 64kb User : maxwell
[VHDL-FPGA-Verilog] pit8253 DL : 0: this is a code of 8253 programme interval timer in verilog
Date : 2025-07-01 Size : 1kb User : dev
[STL] cshiyan2012 DL : 0: 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware description language verilog design complete shift of the frequency divider, timer, serial output, pseudo-code generator, the QPSK the I/Q modulator, QPSK I/Q demodulator based option law IF modulator, and then the individual modules together to form a complete system simulation and its quartusII software.
Date : 2025-07-01 Size : 1.82mb User : 赵旋
[VHDL-FPGA-Verilog] digital-timer DL : 0: 数字时钟的verilog代码，以仿真编译通过，可直接用-Digital clock verilog code which is compiled and simulated and can be directly used
Date : 2025-07-01 Size : 164kb User : 谢文斌
[VHDL-FPGA-Verilog] timer DL : 0: 本代码用verilog语言描述，在nios上操作，实现了定时器的设置和中断操作，并结合timestamp读取程序运行的时间。-The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run.
Date : 2025-07-01 Size : 18.38mb User : 普尔
[VHDL-FPGA-Verilog] ReactionTimer DL : 0: Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.
Date : 2025-07-01 Size : 3kb User : WPI
[VHDL-FPGA-Verilog] 24 DL : 0: 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
Date : 2025-07-01 Size : 1kb User : 单俍
[Other] univ_TIMER DL : 0: verilog source code of programable timer
Date : 2025-07-01 Size : 645kb User : Simon Pruzansky
[transportation applications] traffic-light-Verilog DL : 0: 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights (each including+,- two groups, as the display contents), taking into account the needs of the application, the chip may be required It is connected to the host computer via the I2C interface, to adjust the internal control registers of this Verilog code, comprising led, seg, timer modules.
Date : 2025-07-01 Size : 16kb User : chen le
[Other] apb_timer DL : 0: Verilog code of timer for APB
Date : 2025-07-01 Size : 2kb User : Tan Nguyen
[VHDL-FPGA-Verilog] apb_timer.tar DL : 0: 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
Date : 2025-07-01 Size : 66kb User : megmand