Search - verilog uart code

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[VHDL-FPGA-Verilog] u-uart DL : 0: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Update : 2025-02-17 Size : 5kb Publisher : 李文文
[VHDL-FPGA-Verilog] uart-verilog-vhdl DL : 0: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Update : 2025-02-17 Size : 288kb Publisher : 刘索山
[VHDL-FPGA-Verilog] uart_core_vhdlORverilog DL : 0: 串uart的vhdl，verilog，lattic实现原码里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Update : 2025-02-17 Size : 288kb Publisher : efly
[VHDL-FPGA-Verilog] S6_VGA_change DL : 0: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Update : 2025-02-17 Size : 2.45mb Publisher : 李晨
[assembly language] lcd_module DL : 0: verilog code which receive from uart RX and then output to lcd text display.
Update : 2025-02-17 Size : 2kb Publisher : 蔡俊仪
[Other Embeded program] UART DL : 0: 一个通用串口的verilog源程序，包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
Update : 2025-02-17 Size : 52kb Publisher : typhooncome
[VHDL-FPGA-Verilog] Fusion_UART DL : 0: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Update : 2025-02-17 Size : 3kb Publisher : 张猛蛟
[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar DL : 0: verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码-Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code
Update : 2025-02-17 Size : 38kb Publisher :
[Com Port] uart DL : 0: this a Uart source code using Verilog.
Update : 2025-02-17 Size : 10kb Publisher : Daniel Zhang
[Com Port] uart(Verilog) DL : 0: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Update : 2025-02-17 Size : 10kb Publisher : 陈强
[VHDL-FPGA-Verilog] uart(Verilog) DL : 0: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Update : 2025-02-17 Size : 10kb Publisher : 阿军
[VHDL-FPGA-Verilog] UART DL : 0: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Update : 2025-02-17 Size : 55kb Publisher : 韩思贤
[Com Port] UART DL : 0: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Update : 2025-02-17 Size : 9kb Publisher : 李佳
[VHDL-FPGA-Verilog] fpga_uartrw DL : 0: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Update : 2025-02-17 Size : 54kb Publisher : 蒋斌斌
[VHDL-FPGA-Verilog] mini-uart DL : 0: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Update : 2025-02-17 Size : 248kb Publisher : serein
[Software Engineering] lab3 DL : 0: verilog source code for uart design
Update : 2025-02-17 Size : 534kb Publisher : Krishna
[VHDL-FPGA-Verilog] uart DL : 0: Verilog编写的UART程序源代码。测试成功。支持字符串发送-UART prepared Verilog source code. Successful test. Support string sent
Update : 2025-02-17 Size : 1.48mb Publisher : 卢山
[VHDL-FPGA-Verilog] uart-code-Verilog DL : 0: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Update : 2025-02-17 Size : 10kb Publisher : 李明纬
[VHDL-FPGA-Verilog] uart DL : 0: UART verilog 代码，内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Update : 2025-02-17 Size : 15kb Publisher : dingyy
[VHDL-FPGA-Verilog] uart DL : 0: verilog编写的uart发送和接收的源代码。简单易懂。-verilog uart prepared to send and receive the source code. Straightforward.
Update : 2025-02-17 Size : 468kb Publisher : luoqv

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