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[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[Communication-Mobile] async_fifo.v

Description: the verilog model of async_fifo.
Platform: | Size: 1024 | Author: nightyboy | Hits:

[ARM-PowerPC-ColdFire-MIPS] verilog

Description: 8bit alu use verilog hdl
Platform: | Size: 8192 | Author: 周微微 | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[AI-NN-PR] ANN_weight_connect.v

Description: 用VERILOG语言编写的神经元权值连接的源代码,供大家享用,但是注释很少.-Using Verilog languages neuron weights connected to the source code for everyone to enjoy, but rarely comment.
Platform: | Size: 3072 | Author: yu_leo | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[Streaming Mpeg4] ldpc_encoder_802_3an.v

Description: LDPC 编码的Verilog源代码，我没有验证，不知道效果如何，与大家分享，供大家参考。-LDPC-coded Verilog source code, I did not verify, I do not know how to share with you, for your reference.
Platform: | Size: 622592 | Author: peter | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL-code

Description: verilog 经典例子的源码 非常适用于初学verilog的朋友们-classic example of verilog source code
Platform: | Size: 51200 | Author: 李晨 | Hits:

[Windows Develop] verilog

Description: 里面有一百多个verilog实例 深入浅出的讲述了vrilog硬件描述语言的开发过程 成语代码以word 形式 -There are more than 100 verilog examples described in simple terms vrilog hardware description language code of the development process in order to word the form of idioms
Platform: | Size: 175104 | Author: 魏 | Hits:

[VHDL-FPGA-Verilog] LatticeMico8_v3_0_Verilog

Description: The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
Platform: | Size: 1155072 | Author: 郭豪偉 | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[Embeded-SCM Develop] wm8731_zhengxianbo

Description: 讲诉了如何编写VERILOG程序通过DE2开发板的wm8731芯片产生正弦波-Talk about how to write VERILOG v. procedure DE2 development board wm8731 chip generated sine wave
Platform: | Size: 33792 | Author: xiaopeng | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog program for real time clock.. select the .v file to view the code.
Platform: | Size: 220160 | Author: Arjun | Hits:

[Other] cam_verilog.v.tar

Description: verilog source code for cam functionality
Platform: | Size: 1024 | Author: balu | Hits:

[Other] seqdetector1001.v.tar

Description: 1001 sequence detector in verilog code for mealy state machine
Platform: | Size: 1024 | Author: balu | Hits:

[VHDL-FPGA-Verilog] MEDIAN.v

Description: fpga 的 median的verilog实现-median of verilog implementation
Platform: | Size: 1024 | Author: xyz | Hits:

[Windows Develop] verilog

Description: 包含了许多verilog编程的实用例子，且有运行之后的V文件，很完整-verilog
Platform: | Size: 93184 | Author: 徐军 | Hits:

[VHDL-FPGA-Verilog] LIP1733CORE_system_vbus_arbiter

Description: Verilog V Bus arbiter module
Platform: | Size: 27648 | Author: jc | Hits:

[VHDL-FPGA-Verilog] DAC-use-verilog

Description: 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral description
Platform: | Size: 302080 | Author: 张生 | Hits:
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