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[assembly languagesine

Description: 用verilog语言编的正弦波发生器,可以用QuartusII来打开这个源码,也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[VHDL-FPGA-Verilogsin.tar

Description: 神奇的sin波生成verilog源码,非常简单的代码无需乘法即可生成sin,cos,值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[VHDL-FPGA-Verilogverilog_sine-wave-generator

Description: verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
Platform: | Size: 13312 | Author: 任健铭 | Hits:

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