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[VHDL-FPGA-Verilogvga_gui

Description: 在DE2开发板上实现,由于DE2中的SSRAM只有512K,所以640*480*3(byte)的显存是不够的显示结果是经缩放 后的效果,具体可修改Altera_UP_Avalon_Pixel_Buffer buffer模块中的相关代码。 我把代码移植到DE2-70上后,显示的就很正常了。-In the DE2 development board to achieve, due to the SSRAM DE2 only 512K, so 640* 480* 3 (byte) of memory is not enough to show that the result is scaled by the effect of specific Altera_UP_Avalon_Pixel_Buffer buffer module can modify the relevant code. I put code into DE2-70 on, the display of the normal for the.
Platform: | Size: 29208576 | Author: 张业 | Hits:

[VHDL-FPGA-Verilogvga_gui

Description: VGA 的 ip core 编写程序时需要逐点编写-VGA-ip core programming point by point to write
Platform: | Size: 6821888 | Author: wang | Hits:

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