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Description: 將VHDL設計轉換成Verilog設計的程式
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Size: 17423 |
Author: 黃彥華 |
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Description: 將VHDL設計轉換成Verilog設計的程式-VHDL design will be converted into Verilog design program
Platform: |
Size: 17408 |
Author: 黃彥華 |
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Description: VHDL to verilog converter
Platform: |
Size: 41984 |
Author: sanj |
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Description: vhdl to verilog rtl converter, it support simple vhdl syntax, i think it is very useful
Platform: |
Size: 38912 |
Author: xilei |
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Description: convert VHDL files to Verilog files
Platform: |
Size: 45056 |
Author: hj |
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