Search - vhdl实现除法器

Search - vhdl实现除法器 - List

[Internet-Network] subr DL : 0: VHDL 8位无符号除法器试验报告计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。其实现方法是，将除法器分为两个状态：等待状态与运算状态。开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Update : 2008-10-13 Size : 81.16kb Publisher : aa
[Other resource] vhdl实现除法器 DL : 0: vhdl实现除法器
Update : 2010-10-27 Size : 1.03kb Publisher : sunchao1228
[SourceCode] VHDL除法器 DL : 0: 用vhdl实现除法器，很好用，经过验证!
Update : 2011-11-07 Size : 49.05kb Publisher : 568895323@qq.com
[ISAPI-IE] subr DL : 0: VHDL 8位无符号除法器试验报告计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。其实现方法是，将除法器分为两个状态：等待状态与运算状态。开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Update : 2025-02-17 Size : 81kb Publisher : aa
[VHDL-FPGA-Verilog] DivArrUns DL : 0: 用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted
Update : 2025-02-17 Size : 3kb Publisher : 初德进
[Software Engineering] 353fpga DL : 0: 用vhdl实现的除法器-Achieved using VHDL divider
Update : 2025-02-17 Size : 1kb Publisher : wenhao sun
[VHDL-FPGA-Verilog] djdcf DL : 0: 在3D图像处理等对运算要求高的领域，高效除法器已成为处理器内必不可少的部件。在分析除法器设计的泰勒级数展开算法基础上，提出了一种新的除法器设计算法。在满足同样精度的情况下，所实现的三级流水线的除法器，与基于泰勒级数展开算法的除法器相比，面积更小，速度更快。-In 3D image processing and so on, demanding area of computing, efficient divider has become essential components inside the processor. In analyzing the divider design Taylor series expansion algorithm based on a new design algorithm divider. Meet the same accuracy in the cases, the three realize the divider line, and based on the Taylor series expansion algorithm divider compared to a smaller area, faster.
Update : 2025-02-17 Size : 154kb Publisher : usbusb01
[VHDL-FPGA-Verilog] divider DL : 1: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Update : 2025-02-17 Size : 2kb Publisher : 朱秋玲
[VHDL-FPGA-Verilog] divider DL : 0: 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed divider code, and FPGA hardware platform and tested
Update : 2025-02-17 Size : 1kb Publisher : hewg
[VHDL-FPGA-Verilog] div_aegp DL : 0: 用VHDL语言实现的除法器，可以处理非整除运算。精度0.004-VHDL language used to achieve the divider, you can deal with non-divisible operations. Accuracy of 0.004
Update : 2025-02-17 Size : 1kb Publisher : sunfat
[VHDL-FPGA-Verilog] what DL : 0: 除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助. -Divider can be very good VHDL divider realize the function of great help for beginners.
Update : 2025-02-17 Size : 1kb Publisher : panjun
[VHDL-FPGA-Verilog] baweichufaqi DL : 0: 介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided into several sub-divider module, for each sub-modules were designed, each generation of functional modules to complete the overall design, implementation arbitrary number of 8 unsigned division.
Update : 2025-02-17 Size : 4kb Publisher : 佘斌
[VHDL-FPGA-Verilog] divider DL : 0: 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
Update : 2025-02-17 Size : 1kb Publisher : jh
[VHDL-FPGA-Verilog] Divider DL : 0: 一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
Update : 2025-02-17 Size : 145kb Publisher : maxpayne
[VHDL-FPGA-Verilog] juzhenqufaqi DL : 0: 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
Update : 2025-02-17 Size : 6kb Publisher : helinglin
[VHDL-FPGA-Verilog] divider DL : 0: 8位的除法器。用VHDL语言进行设计实现。-8-bit divider. With VHDL design languages.
Update : 2025-02-17 Size : 5kb Publisher : 张怡萍
[VHDL-FPGA-Verilog] div_8 DL : 0: 八位除法器 VHDL实现八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
Update : 2025-02-17 Size : 1kb Publisher : 郑书鑫
[VHDL-FPGA-Verilog] divider DL : 0: 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
Update : 2025-02-17 Size : 94kb Publisher : 李丽萍
[VHDL-FPGA-Verilog] VHDL DL : 0: 除法器 4位除法器可以编程实现有启发意义-4-bit divider divider can be programmed instructive
Update : 2025-02-17 Size : 50kb Publisher : guoyishi
[VHDL-FPGA-Verilog] chengxu DL : 0: 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
Update : 2025-02-17 Size : 2kb Publisher : 郭慧

« 12 »