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[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] gh_uart_16550_080407

Description: FPGA开发中常用的串口模块，经过本人调试，非常实用-Commonly used in FPGA development serial module, after I debug, very useful
Platform: | Size: 16384 | Author: libin | Hits:

[VHDL-FPGA-Verilog] uart16550.tar

Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Platform: | Size: 246784 | Author: 姓名 | Hits:

[Com Port] uart

Description: uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
Platform: | Size: 257024 | Author: dannel218 | Hits:

[Com Port] uart16750_latest.tar

Description: Implements a 16550/16750 UART core
Platform: | Size: 100352 | Author: Arun | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[Com Port] a_vhd_16550_uart_latest.tar

Description: 16550 uart vhdl source code
Platform: | Size: 119808 | Author: mss | Hits:

[Com Port] uartic

Description: 16550 datasheet for vhdl design
Platform: | Size: 307200 | Author: 王者 | Hits:

[VHDL-FPGA-Verilog] a_vhd_16550_uart

Description: 兼容16550 uart，使用fpga实现，支持多平台-Compatible with 16550 uart, use fpga implementation, multi-platform support
Platform: | Size: 146432 | Author: 东 | Hits:

[Com Port] a_vhd_16550_uart_latest.tar

Description: 实现通用16550的uart的功能模块，使用vhdl编程语言。-16550 uart achieve universal functional modules using vhdl programming language.
Platform: | Size: 119808 | Author: 刘升鹏 | Hits:

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