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[VHDL-FPGA-Verilog] ntsc_gen DL : 0: NTSC信号发生器VHDL源码。输出为BT656格式-NTSC signal generator VHDL source code. BT656 format output
Update : 2025-02-17 Size : 1kb Publisher : 吕奔
[Graph program] rgb2ycrcb DL : 0: 真正可用的RGB转YCbCr的verilog程序，输出格式为标准BT.656格式，经本人亲自编写并验证，可在硬件上正常工作。-Truly available to the Verilog RGB to YCbCr procedures BT.656 output format as the standard format, as I personally prepared and verified in the hardware work correctly.
Update : 2025-02-17 Size : 2kb Publisher : cloud
[Video Capture] camera_up DL : 0: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Update : 2025-02-17 Size : 32kb Publisher : 孙喆
[ActiveX/DCOM/ATL] CCIR656 DL : 0: CCIR656(BT656)标准 ITU-R Recommendation 656 - Standard Text -ITU-R Recommendation 656- Standard Text
Update : 2025-02-17 Size : 12kb Publisher : 李志双
[VHDL-FPGA-Verilog] d1_dec DL : 0: d1(BT.656) video decoder VHDL code
Update : 2025-02-17 Size : 1kb Publisher : thorn