Search - vhdl 7-seg

Search - vhdl 7-seg - List

[Other resource] seg DL : 0: 7段数码管显示的VHDL语言，适合初学者用，相当不错的
Update : 2008-10-13 Size : 799byte Publisher : 土波
[VHDL-FPGA-Verilog] seg DL : 0: 7段数码管显示的VHDL语言，适合初学者用，相当不错的-7 digital tube display VHDL language, suitable for beginners to use, fairly good
Update : 2025-02-17 Size : 1kb Publisher : 土波
[VHDL-FPGA-Verilog] 7vhdl DL : 0: 16 进制段位数码译码扫描显示，用VHDL编写计数器并完成计数显示-16-band digital decoding scan revealed Dan, using VHDL to prepare and complete the count of counter display
Update : 2025-02-17 Size : 60kb Publisher : wang
[Windows Develop] display4-7 DL : 0: 7段译码器本压缩文件含有2个程序，一个是共阴极的，一个是共阳极的，方便大家不同的试验箱使用-Decoder paragraph 7 of the compressed file contains two procedures, a total of cathode, a total of anode to facilitate the use of different chamber
Update : 2025-02-17 Size : 1kb Publisher : 吴明星
[VHDL-FPGA-Verilog] counter_clk DL : 0: 是vhdl语言，在fpga开发板上实现十进制技术（7段数码管显示），包括复位，清零，计数使能。-Is the VHDL language, in the FPGA development board realize decimal technology (7 digital tube display), including reset, cleared, counting enable.
Update : 2025-02-17 Size : 1.86mb Publisher : 李秀艳
[Other] 7-LED DL : 0: 如题目所示，将二进制码转换为7位LED显示-Such as the title indicates, will be converted into binary code 7 LED display
Update : 2025-02-17 Size : 1kb Publisher : wxw_s_life
[SCM] scan_LED DL : 0: 1）输入设备为4*4矩阵键盘，分别代表0~F； 2）输出设备为四位数码显示管，初始值显示0000，当按下某一键时，最右边的一位数码显示管显示最新一次所按按键的数值，而之前的显示值左移，例如，第一次按‘1’键，则显示0001；第二次按‘3’键，则显示0013；第三次按‘5’键，则显示0135；第四次按‘7’键，则显示1357；第五次按‘9’键，则显示3579，第四次按‘F’键，则显示579F-1) input device for the 4* 4 matrix keyboard, representing 0 ~ F 2) output device for the four digital display tubes, showed that the initial value of 0000, when the press of a button, it is the right of possession of a digital display according to the latest show by the numerical keys, and left before the display value, for example, the first time by the' 1 ' key, it shows 0001 the second time by the' 3' key, it shows 0013 the third time in accordance with' 5 ' button, it shows 0135 the fourth time by the' 7 ' key, it shows 1357 the fifth time by the' 9' key, it shows 3579, the fourth time by the ' F' keys, and so showed 579F
Update : 2025-02-17 Size : 195kb Publisher : 王广玉
[VHDL-FPGA-Verilog] 7-seg-display DL : 0: 数码管动态显示程序，使用VHDL编写的程序，可移植性好-Digital dynamic display program, the use of VHDL procedures, portability
Update : 2025-02-17 Size : 1kb Publisher : lsw
[Software Engineering] Top_LED_TUBE DL : 0: It is a timer VHDL code. The outputs are designed for 7-seg display.
Update : 2025-02-17 Size : 2kb Publisher : Mahpa