Search - vhdl 74LS160

[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[VHDL-FPGA-Verilog] 74LS160

Description: 一个很实用的74系列的VHDL源码实例，可以很容易的学会VHDL语言-A series of 74 practical examples of VHDL source code, you can easily learn to VHDL language
Platform: | Size: 64512 | Author: dalchan | Hits:

[VHDL-FPGA-Verilog] 74LS160

Description: 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
Platform: | Size: 50176 | Author: 周 | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] 74ls160

Description: 这是一个使用vhdl语言编写的74LS160计数器，具有同步置位，异步清零的功能。-This is a use vhdl language 74LS160 counter with synchronous set, asynchronous clear function.
Platform: | Size: 38912 | Author: | Hits:

[VHDL-FPGA-Verilog] 74LS160jishuqi

Description: 74ls160十进制可预置计数器VHDL语言代码-74ls160 decimal VHDL language code can be preset counter
Platform: | Size: 1024 | Author: syt | Hits:

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[VHDL-FPGA-Verilog] bhgfdti

[VHDL-FPGA-Verilog] 74LS160

[VHDL-FPGA-Verilog] 74LS160

[VHDL-FPGA-Verilog] vhdlcoder

[VHDL-FPGA-Verilog] 74ls160

[VHDL-FPGA-Verilog] 74LS160jishuqi

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