Search - vhdl 8 bit binary

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[SCM] VHDL范例 DL : 0: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Date : 2025-07-02 Size : 42kb User : kerty
[VHDL-FPGA-Verilog] mutip DL : 0: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Date : 2025-07-02 Size : 1kb User :
[VHDL-FPGA-Verilog] tushuguan DL : 0: --功能描述 --1 刷卡后产生与本人身份唯一对应的串行二进制码元序列，作为模拟系统的输入信号（此处不妨设为8位学生学号）。 --2 经过串并转换，序列变成一个8位二进制数。 --3 遍历预先存储在rom中的学号信息，逐一和这个8位数相比较，如果有相匹配的信息，显示欢迎字样（此处用一个高电平表示），同时打开栅栏门（也用一个高电平表示）。 -- Functional Description- 1 credit card and identity generated only the corresponding element of the serial binary code sequence, as a simulation system of the input signal (in this case may be set to No. 8 students).- 2 after a string and conversion into a sequence of 8-bit binary number.- 3 pre-stored in the rom traversal of the Student ID information, one by one and compared to the 8-digit, if there is match the message that welcomes the word (here, said with a high), at the same time open the gate ( also expressed a high level).
Date : 2025-07-02 Size : 1kb User : leizi
[VHDL-FPGA-Verilog] shifter DL : 0: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Date : 2025-07-02 Size : 126kb User : 623902748
[Other] 8-bit_multiplier DL : 0: 用ASM原理做二進位8-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
Date : 2025-07-02 Size : 1kb User : 沉默劍士
[Windows Develop] Sequencedetector DL : 0: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output.
Date : 2025-07-02 Size : 4kb User : yufang
[VHDL-FPGA-Verilog] vhdllock DL : 0: 用vhdl设计的8位二进制串行密码锁，设计简单实用-Vhdl design with 8-bit binary serial lock design is simple and practical
Date : 2025-07-02 Size : 2kb User : liuyunyu
[VHDL-FPGA-Verilog] HexToBin DL : 0: How to transform a binary 4 digit number into a 8 bit number for a seven segment display, characters 0 to 15 i.e. Hexadecimal.
Date : 2025-07-02 Size : 306kb User : Basil
[VHDL-FPGA-Verilog] sy4 DL : 0: 用VHDL语言设计了一个8位2进制全加器-VHDL language design with an 8-bit binary full adder 2
Date : 2025-07-02 Size : 169kb User : 杨帆
[Software Engineering] serial-adder DL : 0: VHDL code for adding two hard-coded 8-bit binary numbers
Date : 2025-07-02 Size : 8kb User : harsha
[Software Engineering] 8-jinzhi-counter DL : 0: 8进制计数器每计数八次进一次位，vhdl语言的基础程序，对初学者很有帮助-8 binary counter into a bit of each of eight counts, vhdl language based program, very helpful for beginners
Date : 2025-07-02 Size : 1kb User : zhaohong
[VHDL-FPGA-Verilog] cc14585 DL : 0: 用vhdl语言编译一个8位二进制求补器对输入的数字进行求补运算-Vhdl language compiler with an 8-bit binary complement of the input device to complement the number of operations
Date : 2025-07-02 Size : 282kb User : 宋子皓
[VHDL-FPGA-Verilog] complement DL : 0: 用vhdl语言编译一个8位二进制求补器实现求补运算-Vhdl language compiler with an 8-bit binary complement complement computing device to achieve
Date : 2025-07-02 Size : 291kb User : 宋子皓
[VHDL-FPGA-Verilog] Counter60min DL : 0: VHDL语言编写的一个六十进制计数器（用于分钟），一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。-A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit output. It is one of my total 9 modules that are used to design a digital clock.
Date : 2025-07-02 Size : 203kb User : chzhsen
[Other] 32counter DL : 0: 用VHDL语言设计一个32位二进制计数器并进行功能仿真 2.用VHDL语言设计一个8位数码扫描显示电路 -A 32-bit binary counter design using VHDL language and functional simulation using VHDL language design an 8-bit digital scanning display circuit
Date : 2025-07-02 Size : 40kb User : 陈舒
[Other] 8bit-multiplier DL : 0: 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of the multiplicand 1, the multiplier the left after the last and addition if it is 0, to 0 after adding the left until the most significant bit of the multiplicand.
Date : 2025-07-02 Size : 2kb User : 李谦
[Other] VHDL-basedAD0809 DL : 0: 使用VHDL语言编写的AD0809驱动程序，输入0 ~5V的电压，输出8位二进制代码，0V对应“00000000”，5V对应“11111111”。-Using VHDL language AD0809 driver, enter 0 ~ Voltage of 5V, output 8-bit binary code, 0V corresponds to 00000000 , 5V corresponds to 11111111.
Date : 2025-07-02 Size : 206kb User : 于润伟
[VHDL-FPGA-Verilog] Serial-input--parallel-output DL : 0: 关于VHDL的一个问题。串行输入64位二进制数，要求把数据按每8位存在8个寄存器中并行输出-A question about the VHDL. Serial input 64-bit binary number is required for every eight data registers the presence of eight parallel outputs
Date : 2025-07-02 Size : 1kb User : 龙
[ARM-PowerPC-ColdFire-MIPS] vivado DL : 0: 用中规模MSI基本逻辑功能模块实现关模比较器（要求分别使用中规模和语言实现）：功能要求：它的输入是两个8位无符号二进制整数X和Y，以及一个控制信号S；输出信号为1个8位无符号二进制整数Z。输入输出关系为：当S=1时， Z=min(X,Y)；当S=0时， Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).)
Date : 2025-07-02 Size : 10kb User : 瘾1581