Search - vhdl MOD

[VHDL-FPGA-Verilog] mt48lc8m16a2

Description: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
Platform: | Size: 6144 | Author: hxwf801 | Hits:

[VHDL-FPGA-Verilog] Intel8251

Description: 用VHDL实现Intel 8251的UART功能-Intel 8251 with VHDL realization of the UART Function
Platform: | Size: 243712 | Author: | Hits:

[VHDL-FPGA-Verilog] Am29lv160d

Description: 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding pdf documentation.
Platform: | Size: 216064 | Author: 天策 | Hits:

[Other] vhdlcodes

Description: with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this site also.i really needed codes please accept that as soon as possible.
Platform: | Size: 2048 | Author: nitin | Hits:

[Program doc] mod

Description: explain all the modulation techniques so u can understand them very clearly
Platform: | Size: 402432 | Author: qais | Hits:

[ADO-ODBC] Leopard_Mods_On_XP_by_kampongboy92

Description: este documento es para vhdl
Platform: | Size: 14584832 | Author: nenemillion | Hits:

[Crack Hack] BasicRSA_latest.tar

Description: RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key
Platform: | Size: 5120 | Author: nb | Hits:

[VHDL-FPGA-Verilog] MT29FxxG08xx

Description: MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。-MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed description, testing proved very accurate.
Platform: | Size: 92160 | Author: wuyihua | Hits:

[Other] cnt8

Description: 用JK-flip-flop做的8进制counter-mod-8-counter
Platform: | Size: 385024 | Author: suhang | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

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