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[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[Other Embeded program] cp2102(chinese)

Description: 单芯片 USB 转 UART 数据转换器 - 集成的 USB 收发器无需外部电阻 - 集成的时钟无需外部振荡器 - 集成的 512 字节 EEPROM 用于为供应商代码产品代码序列号功率标牌版本号和产品描述等数据提供存储空间 - 片内上电复位电路 - 片内电压调节器3.3V 输出 USB 功能控制器 -符合USB 规范 2.0 全速 (12 Mbps) -通过SUSPEND 和 RI 引脚支持的USB中止状态-Single-Chip USB to UART Data Transfer 􀁺 Integrated USB transceiver no external resistors required 􀁺 Integrated clock no external crystal required 􀁺 Integrated 1024-Byte EEPROM for vendor ID, product ID, serial number, power descriptor, release number, and product description strings 􀁺 On-chip power-on reset circuit 􀁺 On-chip voltage regulator: 3.3 V output 􀁺 100 pin and software compatible with CP2101 USB Function Controller 􀁺 USB Specification 2.0 compliant full-speed (12 Mbps) 􀁺 USB suspend states supported via SUSPEND pins
Platform: | Size: 173056 | Author: lin | Hits:

[VHDL-FPGA-Verilog] 6soft_247MHz_channel

Description: lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟 input_buffer.vhd 输入控制 ri_addr_gen.vhd ri信息提取 ul_common_pack.vhd 变量定义 write_ram.vhd 解交织 deintlv_data.txt 数据源 deintlv_data_ack.txt ack信息源 deintlv_data_cqi.txt cqi信息源 deintlv_data_ri.txt ri信息源 sim_lib.tcl altera库编译 ue.tcl modelsim 脚本-upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
Platform: | Size: 200704 | Author: renliang | Hits:

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[VHDL-FPGA-Verilog] risc_cpu

[Other Embeded program] cp2102(chinese)

[VHDL-FPGA-Verilog] 6soft_247MHz_channel

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