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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
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Size: 2048 |
Author: 张键 |
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Description: FPGA控制AIC23实现音频信号处理。AIC23是TI公司的高性能立体声处理芯片。-FPGA realization of the control AIC23 audio signal processing. AIC23 is a stereo TI' s high-performance processing chip.
Platform: |
Size: 1456128 |
Author: |
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