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原创VERILOG HDL 实现CACHE的操作,有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Update : 2025-02-17 Size : 4kb Publisher : MingCheng

实现乒乓缓存,用verilog语言编写!-Realize cache ping-pong, using Verilog language!
Update : 2025-02-17 Size : 162kb Publisher : zhl

高质量的VHDL代码乒乓处理FIFO缓存-High-quality VHDL code deal with ping-pong FIFO cache
Update : 2025-02-17 Size : 1kb Publisher : wode

VGA模块的VHDL代码和软件驱动,可作为外设挂接在Avalon总线上。用一块SRAM作为显存,双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
Update : 2025-02-17 Size : 6kb Publisher : ctqy

本文主要介绍的是采用直接数字频率合成的短波信号发生器,它主要以微电脑控制部分、直接数字频率合成(DDS)部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作,操作方便明了,增加了很多功能。它通过启动DDS后,把内存缓存区的数据送到DDS后输出相应的频率,并把数据转换为BCD码,送到液晶显示器进行显示。该系统输出稳定度、精度极高,适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Update : 2025-02-17 Size : 456kb Publisher : xiang

DL : 0
MEMORY CACHE SIMPLE CODE
Update : 2025-02-17 Size : 12.25mb Publisher : anaterremoto

本文给出了一个cache的所有源代码,存为txt格式的压缩包-this is a code of a cache
Update : 2025-02-17 Size : 1kb Publisher : 张的的
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